We're developing a couple 3U OpenVPX PCIe peripheral boards. I have a Cyclone V GT Dev Kit, but can't locate any information on drivers used to Tx/Rx data and configuration for the PCIe HardIP interface. Any guidance to design examples and documentation is most appreciated.
Currently I am reviewing the forum for any open questions and found this thread. I apologize that no one seems to answer this question that you posted. Since it has been a while you posted this question, I'm wondering if you have found the answer? If not, please let me know, I will try to assign/find someone to assist you. Thank you.
For PCIe example design, you can refer to AN456, however, there is no much information on driver and which usually need to develop by user.
Perhaps you can take a look the PCIe Linux driver source files are available at these wiki links:
Unfortunately, Linux drivers aren’t going to be helpful as we’re gearing the design for a Win10 OS DoD customer. Do you know of a Win10 driver example?
Here are some additional questions we have:
PCIe Hard IP
* I believe that the Cyclone PCIe Hard IP supports either Dynamic Clock Recovery (DCR) or the use of a 100 MHz Reference Clock. Is this a correct understanding?
* From what I’ve been told, OpenVPX is moving away from the use of a Ref Clock.
* Are there any issues with DCR operation from either a Tx or Rx standpoint?
* What option does Altera recommend for ease of use?
* If a Ref Clock is used, is there any limitation or restriction on which Ref Clock pin on the FPGA Transceiver banks the clock is attached to?
Software Driver & DMA
* I can’t find any information regarding the software driver Intel/Altera uses to communicate with the PCIe Hard IP in the Cyclone V.
* Does Altera have such a driver?
* If so, where is it located so I can download it from their website?
* How is DMA enabled in the Hard IP and how is it configured?
* Are there Rx/Tx FIFOs in the Hard IP and does the user have control over FIFO Almost Full or Almost Empty signaling?
* I’m interested in taking training courses on Creating PCI Express Links Using FPGAs (IPCIE) <
https://www.intel.com/content/www/us/en/programmable/support/training/course/ipcie.html> and Advanced Qsys System Integration Tool Methodologies (IQSYS102) <https://www.intel.com/content/www/us/en/programmable/support/training/course/iqsys102.html
> but both are showing no classes are scheduled.
* Any possibility of getting the course materials for these so I can self-study?
FPGA Configuration Options
* Looking for a recommendation of the latest best practices on configuration.
* In the past, I’ve always used single-bit serial devices (EPCS type) for FPGA configuration using AS configuration
* I see that there are 3rd party four-bit serial devices (EPCQ type) now.
* I also see the Flash/Max example on Cyclone V DVK I purchased that use a 16b parallel flash in conjunction with a MAX V
* Do you or Intel/Altera have a recommendation for FPGA configuration? I’d like to keep the configuration as simple and straightforward as possible. We have no issues with time for configuration (unless addl constraints are required for the use of PCIe Hard IP), so serial single-bit is fine unless you recommend otherwise.
For PCIe DMA example, you can refer to the AN690. As I can see, it came with linux and window application driver, but the detail information of how to create the driver is not available.
The PCIe support 100Mhz reference clock, you can locate it closer to the transceiver bank of PCIe, I don’t see the DCR option as reference clock is available in user guide, please share with us if there is a document mentioned cyclone V support DCR as reference clock. As for the Instructor-Led courses, you can try to request a class in your region (from the bottom of the link).
In term of configuration, it is up to the designer to decide base on their requirement, if there is no concern of the configuration time, then you may just choice the method that you are familiar and comfortable. Perhaps, you can open a new thread to discuss this in detail if needed.