Dual ported ram in modelsim

Altera_Forum · ‎03-13-2009

I have problems accessing dual ported ram in Modelsim.

My ram looks like this:

component ram_megafunction is

port

(

address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

clock : IN STD_LOGIC ;

data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

rden_a : IN STD_LOGIC := '0';

rden_b : IN STD_LOGIC := '0';

wren_a : IN STD_LOGIC := '0';

wren_b : IN STD_LOGIC := '0';

q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);

q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)

);

end component;

when i write the following:

data_in <= "10101010101010101010101010101010";

the resulting data_out is "X0X0X0X0X0X0X0X0X0X0X0X0X0X0X0X0";

What i am doing wrong?

(Sorry for my bad english)

Altera_Forum · ‎03-13-2009

It seems that you have multiple drivers on some signals. Forcing a signal to 0 and 1 at the same time will give an X.

You can check a few things:

- do you have only one connection on data_a and data_b?

- are you trying to write two different values from each port at the same address?

- do you have only one connection to data_out?

Altera_Forum · ‎03-13-2009

Ok, thank you, i have found the problem.

data_out was driven twice.