Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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EDA Netlist Writer Crash with SystemVerilog

Altera_Forum
Honored Contributor II
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Hi, 

I'm getting frequent crashes part way through the EDA Netlist Writer phase of compiles. This only seems to occur using SystemVerilog output - never seen it with plain Verilog projects. Occurs both with Q14.0 and 17.1. Fixed by doing a 'clean', but returns on next or next plus one compile - meaning if I remember to do a 'clean' it takes maximum time. Any ideas, anyone?
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