Honored Contributor II
01-19-2018 06:05 PM
Hi,I'm getting frequent crashes part way through the EDA Netlist Writer phase of compiles. This only seems to occur using SystemVerilog output - never seen it with plain Verilog projects. Occurs both with Q14.0 and 17.1. Fixed by doing a 'clean', but returns on next or next plus one compile - meaning if I remember to do a 'clean' it takes maximum time. Any ideas, anyone?