I'm getting a hold time violation on all signals in my project. After carefully checking the TimeQuest Timing Reports and comparing them to the other projects I found that my report doesn't have the "clock pessimism removed" line. So I suppose that the common clock path pessimism removal in not enabled in the project. I'm trying to find where I can enable it in Quartus, but with no success till now.
I'm working with Quartus 16.1. In older versions it was in Assignments -> Settings -> TimeQuest Timing Analyzer, but in this version I can't find this setting...
The option no longer exists in newer versions of Quartus. Removing the pessimism would not be the solution for timing issues even if the option was still available. There must be another reason(s) why you are seeing hold timing violations. Make sure you're analyzing hold timing using a fast corner timing model, and make sure you have the Optimize Hold Timing advanced Fitter setting enabled (it's on by default, but check to make sure).
Thank you @sstrell ,
1. The Optimize Hold Timing advanced Fitter setting is enabled.
2. Clock paths for Data Arrival Path and for Data Required Path have a common PLL. On-Die Variation makes use of a slow and fast sub-models for it. However, since the PLL is common for both paths, Common Clock Path Pessimism should remove these on-die variations. Checking my another design in a similar situation, I can see "clock pessimism removed" line in the Timing Report and no timing issues. But in this specific design I don't see this line which causes the hold time violation.
The design was initialized in an older Quartus version by someone who doesn't work here anymore, so probably he has disabled pessimism removal option. How can I fix it?