- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
In my test bench I have the following
architecture test of test_limiter is
...
signal high_limit_led :std_logic_vector(3 downto 0);
signal low_limit_led :std_logic_vector(3 downto 0);
...
component limiter is
port(limit_low, limit_high, input :in std_logic_vector(3 downto 0);
limit_low_led,limit_high_led,input_led : out std_logic_vector(3 downto 0);
limit_high_display, limit_low_display, input_display : out std_logic_vector(6 downto 0);
output : out std_logic_vector(6 downto 0);
led_high, led_low : out std_logic);
end component limiter;
begin
dut: limiter port map(..., input => test_input, low_limit_led => limit_low_led, high_limit_led => limit_high_led, ...);
however when I try to compile this I keep getting this error: Error (10349): VHDL Association List error at test_limiter.vhd(30): formal "low_limit_led" does not exist Please help. I've tried retyping all my other signals as well as just that signal and all of them are fine but that one... I have many of them before and after it but I can not figure it out.
Link Copied
2 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start --- In my test bench I have the following
architecture test of test_limiter is
...
signal high_limit_led :std_logic_vector(3 downto 0);
signal low_limit_led :std_logic_vector(3 downto 0);
...
component limiter is
port(limit_low, limit_high, input :in std_logic_vector(3 downto 0);
limit_low_led,limit_high_led,input_led : out std_logic_vector(3 downto 0);
limit_high_display, limit_low_display, input_display : out std_logic_vector(6 downto 0);
output : out std_logic_vector(6 downto 0);
led_high, led_low : out std_logic);
end component limiter;
begin
dut: limiter port map(..., input => test_input, low_limit_led => limit_low_led, high_limit_led => limit_high_led, ...);
however when I try to compile this I keep getting this error: Error (10349): VHDL Association List error at test_limiter.vhd(30): formal "low_limit_led" does not exist Please help. I've tried retyping all my other signals as well as just that signal and all of them are fine but that one... I have many of them before and after it but I can not figure it out. --- Quote End --- low_limit_led & limit_low_led? aren't you confusing yourself with such naming? I believe you meant: limit_low_led => low_limit_led; instead of low_limit_led => limit_low_led
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start --- low_limit_led & limit_low_led? aren't you confusing yourself with such naming? I believe you meant: limit_low_led => low_limit_led; instead of low_limit_led => limit_low_led --- Quote End --- Oh opps thank you so much.

Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page