so this is one of my first VHDL codes...
(havent finished the cnt select part on the bottom^^)
I get some "10500 vhdl Syntax error"s between 'begin' and 'with cnt select'... But why?? :(:confused:
I can't find anything missing ._.
library ieee;
use ieee.std_logic_1164all;
entity helloworld is
port(key0: IN STD_LOGIC;
Hex0: OUT STD_LOGIC_VECTOR(6 downto 0)
);
end helloworld;
architecture behaviour of helloworld is
signal a: STD_LOGIC;
signal cnt: STD_LOGIC := '0';
begin
a <= not key0;
if a = '1' then
cnt <= cnt + 1;
end if;
if cnt = '16' then
cnt <= '0';
end if;
with cnt select
.
.
.
end behaviour;
