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Altera_Forum
Honored Contributor I
818 Views

Error 10500 Help me !!!

so this is one of my first VHDL codes... 

(havent finished the cnt select part on the bottom^^) 

 

I get some "10500 vhdl Syntax error"s between 'begin' and 'with cnt select'... But why?? :(:confused: 

I can't find anything missing ._. 

 

library ieee; 

use ieee.std_logic_1164all; 

 

entity helloworld is 

port(key0: IN STD_LOGIC; 

Hex0: OUT STD_LOGIC_VECTOR(6 downto 0) 

); 

end helloworld; 

 

architecture behaviour of helloworld is 

 

signal a: STD_LOGIC; 

signal cnt: STD_LOGIC := '0'; 

 

begin 

a <= not key0; 

 

if a = '1' then 

cnt <= cnt + 1; 

end if; 

 

if cnt = '16' then 

cnt <= '0'; 

end if; 

 

with cnt select 

 

end behaviour;
0 Kudos
3 Replies
Altera_Forum
Honored Contributor I
56 Views

if statements must be in a procedural block of code - like a process

Altera_Forum
Honored Contributor I
56 Views

Also, it should be: use ieee.std_logic_1164.all;

Altera_Forum
Honored Contributor I
56 Views

@Tricky: 

Oh thanks a lot , that must be the mistake^^ I didn't realize that as I'm more used to write in C. 

I'll try again now :) 

 

@sstrell: 

Thank you but this mistake is only here in the Thread from typing.
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