Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Error (11238): The following 1 fractional PLL locations are already occupied, and the Fitter cannot merge the previously placed nodes with these instances. The nodes may have incompatible inputs or parameters.



I am working on Cyclone V GT(5CGTFD9EF35C7N) FPGA on quartus. The project was developed by one of the senior student, I am continuing the project left half way through. It is giving me Fitter issues when I try to modify the value of the PLL.


The project has 2 PLL. Both of them are given the reference frequency of 50 MHz. For some reason whenever I try to change the frequency value for the fractional PLL from the archived file of previous version, it gives me errors. But whenever I run it as it is without any modification to the archived project, it doesn't throw any errors on PLL. It says that it cannot merge the fractional PLL whereas in the resource section I can see that only 2/8 fractional PLL is used. I am assuming that the tool understands that they both are different, or should I be doing any assignments to tell the software about it?


Please let me know if any one has the solution to this, I have been trying to fix this issue since last 3 weeks. I have also attached the screen shot for this.


Thank you for the help.

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2 Replies
Valued Contributor II

Have you tried this solution to a similar issue with Fractional PLLs ?


To work around the issue, either move the PLL to a different location where there are sufficient GCLK or RCLK resources or change your PLL compensation mode to Direct compensation mode.

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 The above error attached is an generic error, I am requesting to check the IO assignment and PLL constrain in the qsf file.




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