Error(13264): Can't resolve multiple constant drivers for net "s_wr_data[71][239]"

Altera_Forum · ‎01-25-2018

hi,

when i compile following code,quartus reported a error—— "Error(13264): Can't resolve multiple constant drivers for net "s_wr_data[71][239]" "

this problem puzzled me some time,how do i to sovle this problem?

Thanks in advance and best regards!

the code is as following:


parameter   NUM_CE = 8; 
parameter   NUM_BLOCK = 80;
reg         s_wr_data;
reg    s_wr_en;
genvar i;
generate
for (i=0;i<NUM_CE;i=i+1)
begin:WR_CTRL
//write
        always @( *)
        begin
           case(I_conv_mod)
               4'd0:begin
                   if(loop_i==10'd0)begin
                      s_wr_data           = s_wr_ofmap_data_c1;
                      s_wr_en  = s_wr_ofmap_en_c1;                             
                   end
                   else if(loop_i==10'd1)begin
                      s_wr_data           = s_wr_ofmap_data_c1;
                      s_wr_en  = s_wr_ofmap_en_c1;                             
                   end
                   else if(loop_i==10'd2)begin
                    s_wr_data           = s_wr_ofmap_data_c1;
                      s_wr_en  = s_wr_ofmap_en_c1;                             
                   end
                   else if(loop_i==10'd3)begin
                      s_wr_data           = s_wr_ofmap_data_c1;
                      s_wr_en  = s_wr_ofmap_en_c1;                             
                   end                         
                   else if(loop_i==10'd4)begin
                      s_wr_data           = s_wr_ofmap_data_c1;
                      s_wr_en  = s_wr_ofmap_en_c1;                             
                   end
                   else if(loop_i==10'd5)begin
                      s_wr_data           = s_wr_ofmap_data_c1;
                      s_wr_en  = s_wr_ofmap_en_c1;                             
                   end
                   else begin
                      s_wr_en  = s_wr_en;                             
                   end                         
               end
        4'd1:begin
                   if(loop4_3d==10'd0)begin
                        s_wr_en = {s_wr_ofmap_en2,s_wr_ofmap_en1,s_wr_ofmap_en0}; //0~7
                        s_wr_data  = s_wr_ofmap_data0;
                        s_wr_data  = s_wr_ofmap_data1;
                        s_wr_data  = s_wr_ofmap_data2;                         
                   end
                   else if(loop4_3d==10'd1)begin
                        s_wr_en = {s_wr_ofmap_en2,s_wr_ofmap_en1,s_wr_ofmap_en0}; //0~7
                        s_wr_data  = s_wr_ofmap_data0;
                        s_wr_data  = s_wr_ofmap_data1;
                        s_wr_data  = s_wr_ofmap_data2;                         
                   end
                   else if(loop4_3d==10'd2)begin
                        s_wr_en = {s_wr_ofmap_en2,s_wr_ofmap_en1,s_wr_ofmap_en0}; //0~7
                        s_wr_data  = s_wr_ofmap_data0;
                        s_wr_data  = s_wr_ofmap_data1;
                        s_wr_data  = s_wr_ofmap_data2;                         
                   end
                   else begin
                      s_wr_en  = s_wr_en;                             
                   end                    
        end
        4'd2,4'd3,4'd4,4'd5:begin
                   if(loop8_3d==10'd0)begin
                      s_wr_en = {s_wr_ofmap_en4,s_wr_ofmap_en3,s_wr_ofmap_en2,s_wr_ofmap_en1,s_wr_ofmap_en0}; //0~7
                      s_wr_data  = s_wr_ofmap_data0;
                      s_wr_data  = s_wr_ofmap_data1;
                      s_wr_data  = s_wr_ofmap_data2;
                      s_wr_data  = s_wr_ofmap_data3;
                      s_wr_data  = s_wr_ofmap_data4;                         
                   end
                   else if(loop8_3d==10'd1)begin
                      s_wr_en = {s_wr_ofmap_en4,s_wr_ofmap_en3,s_wr_ofmap_en2,s_wr_ofmap_en1,s_wr_ofmap_en0}; //0~7
                      s_wr_data  = s_wr_ofmap_data0;
                      s_wr_data  = s_wr_ofmap_data1;
                      s_wr_data  = s_wr_ofmap_data2;
                      s_wr_data  = s_wr_ofmap_data3;
                      s_wr_data  = s_wr_ofmap_data4;                     
                   end                         
                   else begin
                      s_wr_en  = s_wr_en;                             
                   end                    
        end
        default: begin
            s_wr_en  = s_wr_en;    
        end
       endcase
    end                                      
end    
endgenerate

Altera_Forum · ‎01-25-2018

I can only assume that some of the ranges for s_wr_data in the case statement overlap for different values of i.

each value of i in the generate loop produce parallel always blocks. And assigning the same bit in two always blocks will produce multiple drivers.

You havent posted the declarations of the following: i_conv_mod, NUM_BLOCK_k5_LOOP, NUM_BLOCK_k3_LOOP