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Error(16045): Instance "dummy_0" instantiates undefined entity "arria10_SoC_mSGDMA_dummy_0"

RubenPadial
New Contributor I
791 Views

Hello,

I am working in a project to be familiar with Platform Designer and msgDMA in Intel Arria 10 SoC platform.

I have instantiated 2 msgDMA (ST-MM and MM-ST) and a SoC IPs as well as a dummy custom module between the 2 msgDMA. When I run the compilation I get the error:

Error(16045): Instance "dummy_0" instantiates undefined entity "arria10_SoC_mSGDMA_dummy_0"

To create the dommy IP I have included a new component and defined the entity in vhdl, attached to this message and it was included to the HDL files of the component.

Could anyone help me to find the rootcause?

------------------------------------------

Test setup

Ubuntu desktot 20.04

Quartus Prime Version 22.4.0 Build 94 12/07/2022 SC Pro Edition

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ShengN_Intel
Employee
738 Views

Hi,

 

I had created a platform designer system with 2 MSGDMA and custom module dummy.vhd in between the 2 MSGDMA. Compilation run successfully without error check attached .qar.

Make sure the entity name is correct and matching. Try to create a new custom IP with updated dummy.vhd. It's better also to re-generate the .qsys to get the updated module files.

 

Thanks,

Regards,

Sheng

 

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ShengN_Intel
Employee
649 Views

Hi,

 

Do you have any further concern or consideration?

Does the problem being resolved?

 

Thanks,

Regards,

Sheng

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RubenPadial
New Contributor I
634 Views

Hello @ShengN_Intel ,

 

I'm checking the .qar file.

When I open it, it doesn't includes the .vhdl file.

RubenPadial_0-1713509232804.png

 

and the block only have an Avalon Memory Mapped Agent input port whereas the dummy module has the avalon_sink : in std_logic_vector(31 downto 0) and avalon_source : out std_logic_vector(31 downto 0) inputs. Why are not needed the Avalon Streaming Sink and Source ports?

 

When I run the compilation, "Timing requirements not met" error is given.

 

 

 

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ShengN_Intel
Employee
623 Views

Hi @RubenPadial ,

 

When I open it, it doesn't includes the .vhdl file.

In platform designer system .qsys, right-click dummy_0 -> Edit -> Files, i had put the dummy.vhd file for analyzing check screenshot.

ShengN_Intel_0-1713513395079.png

 

Why are not needed the Avalon Streaming Sink and Source ports?

I had modified the design (attach below) to use both Avalon Streaming Sink  and Avalon Streaming Source check screenshot.

ShengN_Intel_2-1713513686366.pngShengN_Intel_1-1713513604506.png

 

When I run the compilation, "Timing requirements not met" error is given.

Because don't have the .sdc file. This is just a simple design example to show that there's no problem on the dummy.vhd. As mentioned before, make sure to re-generate the platform system to sync with the core file's update.

 

Thanks,

Regards,
Sheng

 

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ShengN_Intel
Employee
494 Views

Hi,


May I know does your problem being resolved? Do you have any further concern or consideration on this thread?


Thanks,

Regards,

Sheng


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