Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15548 Discussions

Error (169058): I/O standard 3.3-V LVTTL on output I/O pin CAN_TX cannot have Termination logic option setting Series 25 Ohm with Calibration

IGonz6
Beginner
1,387 Views

Hi,

 

I was looking ways to reduce the overshoot in a microstrip line where a 3.3 LVCOSMOS driver of a Cyclone III is connected.

 

I have seen two ways of improving this: a clamp diode and and an output termination to match the line impedance. However, my project does not compile when I configure either 25 or 50 Ohm "Output Termination" for my pin. I am not sure if every pin is able to have this feature or only RUP/RDN ones. Even if I use this pins it does not work. The error message is the following:

 

"Error (169058): I/O standard 3.3-V LVTTL on output I/O pin CAN_TX cannot have Termination logic option setting Series 25 Ohm with Calibration"

 

I have tried to change the "I/0 Standard" to another, but it still giving me the same message. Do you know what I am doing wrong?

 

Thanks in advance,

Iván

0 Kudos
1 Reply
SreekumarR_G_Intel
381 Views

Hello there , 

Looks like 3.3 V LVTTL / LVCMOS support the OCT with and without calibration, Refer table 6.3 in cyclone III handbook .

In Cyclone III ,there are only 4 calibration blocks. Each block paired between two banks. For example there is one OCT calibration block in bank 2 which is common for bank 1. Can you please check OCT applied right calibration banks which you have RPU/RDN connected ?

 

Also note from handbook there are " two I/O banks sharing the same calibration block, both banks must have the same VCCIO if both banks enable OCT calibration ".Can you make sure VCCIO is same?

 

Can you also check PCI diode is enabled in the same OCT applied pins ? 

 

Here is link for OCT IP user guide for your reference,

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_oct.pdf

 

In additional to this , there is one more way you can reduce the overshoot is by changing the source drive current :) .

 

Thank you 

Reply