Error (174068) DDR3 IP

[Rajender1]

Hi,

I tried to instantiate DDR3 memory IP using Verilog HDL, TSW14J56EVM and Quartus Prime Standard edition software. During Compilation I am encontering an error as mentioned below:

Error (174068): Output buffer atom
"ddr:UUT|ddr_0002:ddr_inst|ddr_p0:p0|ddr_p0_memphy:umemphy|ddr_p0_new_io_p
ads:uio_pads|ddr_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_arriavgz:altdq_d
qs2_inst|extra_output_pad_gen[0].obuf_1" has port
"SERIESTERMINATIONCONTROL[0]" connected, but does not use calibrated onchip
termination

Could anyone explain me this error and how to resolve the same?

Regards.

Rajender

[AdzimZM_Intel]

Hi Rajender,

Have you run *p0_pin_assingments.tcl script after synthesis compilation?

This tcl script will help to setup the pin setting for the UNIPHY IP.

Regards,

Adzim

[AdzimZM_Intel]

As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.