I followed the Design Steps for CvP Update Mode descripted in the Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide. The base revision is compiled successfully. However the CvP revision is compiled with fitting errors. Quartus can’t merge some input clocks to the core logic with those already placed global clocks.
Below is the error messages for one of the clocks.
Error (175001): The Fitter cannot place 1 global clock driver.
Info (14596): Information about the failing component(s):
Info (175028): The global clock driver name(s): <core logic design name>:<core logic design label>|<core logic input clock port name>~CVP_IPORTCLKENA0
Error (11238): The following 16 clock driver locations are already occupied, and the Fitter cannot merge the previously placed nodes with these instances. The nodes may have incompatible inputs or parameters.
Error (11239): Location CLKCTRL_G12 is already occupied by <input clock pin name>~inputCLKENA0.
I only listed one of the 16 clock locations above. The global clock assigned at Location CLKCTRL_G12 is connected to the core logic input clock in Info (175028) at the design top level. However Quartus fails to merge them.
I have tried both Quartus Prime standard 17.1.1 (build 593) and the latest 18.1.1 (build 646).
Did I miss anything in my design or is this a bug in Quartus?
It looks like you are designing your design with more than the available clock routing on that particular clock source. I would recommend you to move some of the clock to another clock source.
If you need help on resolving the issue then I will need to have your design in order to investigate the root cause.