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Error (175006): There is no routing connectivity between the IOPLL and destination LVDS_CLOCK_TREE

GatisV
Beginner
438 Views

Hi, I'm getting following error when compiling on Linux "Ubuntu 20.04.2 LTS" with Quartus 20.04.0 Build 72.
Project compiles without errors on Windows 10 with the same Quartus version.

Without LVDS pin assignments project compiles on Linux without errors.
This project uses all LVDS available on FPGA. LVDS modules are clocked with external PLL from single ended clock pin.
I had to add ALTCLKCTRL Intel FPGA IP between pll_lvds_u and data_mapper_u on Windows, otherwise I had similar fitter error.


Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IOPLL(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (175001): The Fitter cannot place 1 IOPLL, which is within IOPLL Intel FPGA IP pll_lvds_altera_iopll_1931_przxftq.
Info (14596): Information about the failing component(s):
Info (175028): The IOPLL name(s): lvds_controller_u|pll_lvds_u|iopll_0|altera_iopll_i|c10gx_pll|iopll_inst
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (175006): There is no routing connectivity between the IOPLL and destination LVDS_CLOCK_TREE
Info (175027): Destination: LVDS_CLOCK_TREE lvds_controller_u|data_mapper_u|lvds_u|lvds_0|core|arch_inst|default_lvds_clock_tree.lvds_clock_tree_inst
Info (175013): The LVDS_CLOCK_TREE is constrained to the region (38, 32) to (38, 86) due to related logic
Info (175015): The I/O pad txr2_out[0] is constrained to the location PIN_A12 due to: User Location Constraints (PIN_A12)
Info (14709): The constrained I/O pad is driven by this LVDS_CLOCK_TREE
Error (175022): The IOPLL could not be placed in any location to satisfy its connectivity requirements
Error (175022): The LVDS_CLOCK_TREE could not be placed in any location to satisfy its connectivity requirements
Info (175029): 1 location affected
Info (175029): IOPLL_2A
Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.
Error (16297): An error has occurred while trying to initialize the plan stage.
Error: Quartus Prime Fitter was unsuccessful. 8 errors, 1 warning
Error: Peak virtual memory: 2536 megabytes
Error: Processing ended: Fri Feb 19 09:17:15 2021
Error: Elapsed time: 00:00:44
Error: System process ID: 41550


How can I compile this project on Linux without errors?
Best reagrds,
Gatis

 

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5 Replies
AminT_Intel
Employee
364 Views

Hello,

 

I am sorry to hear you are facing this difficulty on compiling your project on Linux while the compilation was smooth when you run the project on Windows. Did you create your file project on Windows then you transfer it to Linux? If that is the case then you might get this problem because you missed out some files. Make sure your project files are complete and maybe try to open file through Restore Archived Project under Project tab if normal way does not work. I hope this helps.

Thanks.

GatisV
Beginner
362 Views
Hi,
The project was created and compiled on both OS with the same "build.sh" script from generated Tcl. On Windows I used WSL to run the script.
Best regards
AminT_Intel
Employee
327 Views

Hello,

 

I apologize for the late reply. Do you have sample design by any chance? 

 

Thank you.

GatisV
Beginner
287 Views

Hi,

In design I have 6 identical LVDS SERDES IPs. Each LVDS SERDES IP drives 10 LVDS pairs. When I added individual external PLL for every LVDS SERDES IP, I could compile without any errors on both Linux Ubuntu 18.04 and Windows 10. Previously I had one common external PLL for all 6 LVDS SERDES IPs.

Best regards

AminT_Intel
Employee
263 Views

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

 

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