Error 18694 The reference clock on pll "name"

[yy1]

Quartus Version: Quartus Pro 20.4

Device family: Cyclone 10 Gx

Issue : error 18694 The reference clock on pll "name", which feeds an altera lvds serdes ip instance, is not driven by a dedicated reference clcok pin from the same bank.

The design is use clkin_50(50MHz) as input to int_pll ip, int_pll output(20~100MHz) to lvds tx serdes as ref clock

1. I did't assign any pin to specific location, just let software auto assign

2. when I use the same design in Arria 10 and use quaruts standard 18.1, that will be OK, no show any errors. Why this OK, but error occur whe use Cyclone 10 Gx and Quartus Pro 20.4 ?

3. I find the same issue as below, and try to use those two solution, but it still don't work.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/ip/2019/error--18694---the-reference-clock-on-pll--qsystop0-a10tsemacpcs.html

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/component/2020/error-18694---the-reference-clock-on-pll--externalpll-externalpl.html

4. Which pin is correct dedicated reference clcok pin ? I try to assign clkin_50 to AA6, AD3, AA2, AC1, L2, N1...etc, it still don't work. 

[Ash_R_Intel]

Hi,

The IP needs to be regenerated when changing the device or Quartus version.

Regards.

[yy1]

Hi,

The IP have been already regenerated.

[yy1]

Hi @Ash_R_Intel ,

The IP have been already regenerated before routing.

The error message and IP status as attachment.

Regards

[Ash_R_Intel]

Hi,

I tried to recreate the scenario but am not getting the error. First created a project in v18.1, targeted to Arria 10, generated an LVDS SERDES IP instance with internal reference clock and ran the fitter. It ran without any errors.

Next I created another project in v20.4, targeted to Cyclone 10 GX and imported the above created IP .qsys file. The tool asked for the IP upgrade, so followed the steps and did an Auto Upgrade of the IP. Next I regenerated the IP files and ran the fitter. This also passed the Fitter stage without any errors.

In both the project. tool was allowed to do the pin placement automatically.

Is it possible to isolate and provide us the Cyclone 10 GX design portion which is creating the issue?

Regards.

[Ash_R_Intel]

We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you