Error(21961): Input port OE of a "13_TRUE_DIFF_SIGNALING" I/O output buffer <path> is not supported

[PAA]

Hi, 
I am attempting to implement differential bi-directional IO on the HSIO bank with true differential voltage, using the GPIO Intel  FPGA IP for Agilex 5 device A5ED065BB32AE6SR0.

However,  I am getting following error:  
Error(21961): Input port OE of a "13_TRUE_DIFF_SIGNALING" I/O output buffer
"tx_aux_diff_io|gpio_0|core|i_loop[0].altera_gpio_bit_i|output_buffer.obuf_0" is not supported.

I am using Quartus 24.2 for the compilation.
I see that similar error was seen for Arria 10 device: 
https://www.intel.com/content/www/us/en/support/programmable/articles/000086136.html

This signal is used for Display Port Aux channel and we have the recommended IO level conversion from 3.3V to 1.3V on our PCB. 

------------Instantiation code -------------
signal fmc_dp_rx_aux_in : std_logic_vector(0 downto 0);  -- connected to DisplayPort IP
signal fmc_dp_rx_aux_out : std_logic;                                    -- connected to DisplayPort IP
signal fmc_dp_rx_aux_oe : std_logic;                                      -- connected to DisplayPort IP

-- component declaration --
component bidir_diff_io is
port (
dout : out std_logic_vector(0 downto 0); -- export
din : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
oe : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
pad_io : inout std_logic_vector(0 downto 0) := (others => 'X'); -- export
pad_io_b : inout std_logic_vector(0 downto 0) := (others => 'X') -- export
);
end component bidir_diff_io;

-- Instantiations
rx_aux_diff_io : entity bidir_diff_io.bidir_diff_io
port map (
dout => fmc_dp_rx_aux_in,                    --CONNECTED_TO_dout, -- dout.export
din => (others=>fmc_dp_rx_aux_out), --CONNECTED_TO_din, -- din.export
oe => (others=>fmc_dp_rx_aux_oe),    --CONNECTED_TO_oe, -- oe.export
pad_io => fmc_dp_rx_aux_p,                 --CONNECTED_TO_pad_io, -- pad_io.export
pad_io_b => fmc_dp_rx_aux_n             --CONNECTED_TO_pad_io_b -- pad_io_b.export
);

I am attaching the IP as well as the IO assignment details 

Best Regards,
Pushpraj Adhage

[FvM]

Hi,

as far as I understand, TRUE_DIFF_SIGNALING IO-standard doesn't provide bidirectional operation. You may try differential SSTL-12 or differential POD12.

[PAA]

Thanks for a quick reply. I had already checked that the 1.2 SSTL works. 
The problem is that there is no 1.3V SSTL IO standard to select from the Quartus drop down list under Assignment Editor. 
So, as a work around, could you confirm if it would be acceptable to configure the IO to 1.2 SSTL but run it at  1.3V ?
OR could there be any potential issues for damaging the IOs if we configure it at 1.2V,  but connect the IO bank to 1.3V ?
We plan to share the same IO bank with  CSI Tx signals with mipi-dphy, with 'DPHY' as IO standard. 

[PAA]

-edited to delete earlier response-

[FvM]

I don't expect problems with 1.3 V supply and differential SSTL-12.

[PAA]

Thanks.
The only concern which I need to verify on my side is to see if the Voltage swing for the 1.2V SSTL is compatible > Vdiff In(min)  on the other side receiver. 
We can close this topic. 

[AqidAyman_Intel]

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