Error 23098 when compiling Agilex5 GTS PCIe

[danield17]

I tried to create a design with PCIe GTS IP core and SSGDMA on Agilex5 but I got the following error:

One or more blocks are configured incorrectly and will not have the desired functionality. --BCM instance name: hssi_mono_2_1
====Conflict Description 1====

---Rules and User Set Attributes---
Rule: sm_hssi_pcie_ctl_x4::constraint_pf0_pci_type0_bar2_mask_31_1_rule @ hssi_ss_u0.pcie_top_x4_u0.pcie_ctrltop_x4_u0.pcie_ctl_x4_u0 located in file p4/devices/icd_data/falconmesa/sm7/sm_hssi_pcie_ctrltop_x4/bcmrbc/sm_hssi_pcie_ctl_x4.rbc.sv(3284):
hssi_ss_u0.pcie_top_x4_u0.pcie_ctrltop_x4_u0.pcie_ctl_x4_u0.pf0_pci_type0_bar2_enabled == PF0_PCI_TYPE0_BAR2_ENABLED_DISABLED
hssi_ss_u0.pcie_top_x4_u0.pcie_ctrltop_x4_u0.pcie_ctl_x4_u0.pf0_pci_type0_bar2_mask_31_1 == 2097151

---Conflict---
hssi_ss_u0.pcie_top_x4_u0.pcie_ctrltop_x4_u0.pcie_ctl_x4_u0 - sm_hssi_pcie_ctl_x4::constraint_pf0_pci_type0_bar2_mask_31_1_rule
hssi_ss_u0.pcie_top_x4_u0.pcie_ctrltop_x4_u0.pcie_ctl_x4_u0.pf0_pci_type0_bar2_enabled == PF0_PCI_TYPE0_BAR2_ENABLED_ENABLED || hssi_ss_u0.pcie_top_x4_u0.pcie_ctrltop_x4_u0.pcie_ctl_x4_u0.pf0_pci_type0_bar2_mask_31_1 == 0

--BCM instance name: hssi_mono_2_1
====Conflict Description 2====

---Rules and User Set Attributes---
Rule: sm_hssi_top::vcc_hssi_level_mapping_rule @ located in file p4/devices/icd_data/falconmesa/sm7/sm_hssi_top/bcmrbc/sm_hssi_top.rbc.sv(14094):
vcc_hssi_level == VOLTS_0P75V
Rule: sm_hssi_ss::vcc_hssi_level_pcie_mapping_rule @ hssi_ss_u0 located in file p4/devices/icd_data/falconmesa/sm7/sm_hssi_ss/bcmrbc/sm_hssi_ss.rbc.sv(11130):
Rule: sm_hssi_pcie_top_x4::vcc_hssi_level_rule @ hssi_ss_u0.pcie_top_x4_u0 located in file p4/devices/icd_data/falconmesa/sm7/sm_hssi_pcie_top_x4/bcmrbc/sm_hssi_pcie_top_x4.rbc.sv(163):
Rule: sm_hssi_pcie_ctrltop_x4::pcie_rate_rule @ hssi_ss_u0.pcie_top_x4_u0.pcie_ctrltop_x4_u0 located in file p4/devices/icd_data/falconmesa/sm7/sm_hssi_pcie_ctrltop_x4/bcmrbc/sm_hssi_pcie_ctrltop_x4.rbc.sv(130):
hssi_ss_u0.pcie_top_x4_u0.pcie_ctrltop_x4_u0.pcie_ctl_x4_u0.link_rate == LINK_RATE_GEN4

---Derived values---
- sm_hssi_top::vcc_hssi_level_mapping_rule
hssi_ss_u0.vcc_hssi_level == VOLTS_0P75V
hssi_ss_u0.pcie_top_x4_u0.pcie_ctrltop_x4_u0 - sm_hssi_pcie_ctrltop_x4::pcie_rate_rule
hssi_ss_u0.pcie_top_x4_u0.pcie_ctrltop_x4_u0.vcc_hssi_level == VOLTS_0P8V

---Conflict---
hssi_ss_u0.pcie_top_x4_u0 - sm_hssi_pcie_top_x4::vcc_hssi_level_rule
hssi_ss_u0.pcie_top_x4_u0.vcc_hssi_level == VOLTS_0P8V
hssi_ss_u0 - sm_hssi_ss::vcc_hssi_level_pcie_mapping_rule
hssi_ss_u0.pcie_top_x4_u0.vcc_hssi_level == VOLTS_0P75V

No more conflicts detected

Is anyone know how to handle this error?

[Wincent_Altera]

Hi,

May I know which Quartus version that you are using ?

Can you please regenerate the same design in Quartus v24.3 onwards and see if you are still able to see the same error ?

Based on my experience these errors are caused by an invalid combination of reference clock frequency and operating bit rate.
It happened in Quartus v24.1 and v24.2..
These combinations had removed in Quartus® Prime Pro Edition Software v24.3 onwards.

By right it shall work well when you try v24.3.

Regards,

Wincent_Altera

[danield17]

Hi,

I am using Quartus v24.3.
I have currently selected PCIe gen4 x4 with 256-bit interface and a reference clock of 350MHz.
Hopefully, this information helps in understanding the issue.

Regards,
danield17

[Wincent_Altera]

Hi Daniel,

May I know what is the device OPN that you are using for the gen4 design ?
FYI, "5S /6S" device does not support gen4 . if you are using those OPN , the error is expected.
You can use "4S" OPN for gen4

Regards,
Wincent_Altera

[Wincent_Altera]

Hi,

I wish to follow up with you about this forum case.

Do you have any further questions on this matter ? Else do I have your permission to close this IPS ticket ?

Regards,

Wincent_Altera

[danield17]

Hi Wincent,

I appreciate the effort, but the solution isn’t entirely clear to me.

From what I’ve found so far, these errors seem to stem from IP core configurations and connections—possibly even missing ones—that the Fitter doesn’t accept. I still don’t fully understand why the specific errors I encountered were problematic, but after a few changes to the IP configurations, I managed to get rid of them.

For anyone searching for solutions to the specific errors mentioned above:

pf0_pci_type0_bar2_enabled and pf0_pci_type0_bar2_mask_31_1 error – I was able to resolve this by enabling BAR2.

vcc_hssi_level error – I cleared this one by changing the IP configuration from Gen 4 to Gen 3.


I really wish Intel would provide some documentation or clearer error messages to help users better understand the source and meaning of these issues.

Regards,
danield17

[Wincent_Altera]

Hi Daniel,

Is it possible to share your design .qar file here ?
It will give me more visibility to the problem facing by you in order to provide more accurate answer towards the issue.

Meanwhile,
I really wish Intel would provide some documentation or clearer error messages to help users better understand the source and meaning of these issues.
>> meaning of the error is due to an invalid combination of reference clock frequency and operating bit rate. (as mentioned in the earlier reply)

I am using Quartus v24.3.
I have currently selected PCIe gen4 x4 with 256-bit interface and a reference clock of 350MHz.
>> did you try to recreate the project from empty ? or just perform IP upgrade ?
>> I have experience the same issue as yours, by recreate the project in latest version of Quartus it does not appear anymore, this is happen due to Quartus IP improvement and prevent the invalid combination which causing the conflict.

Regards,
Wincent_Altera

[Wincent_Altera]

Hi Daniel,

Any update from my previous reply ? especially on the .qar file.

Regards,

Wincent_Altera

[Wincent_Altera]

Hi Daniel,

Sorry , I miss this message, glad that you are able to resolve the problem.
Will submit an internal ticket to include this in next version of document (subject to change)
Thanks for sharing with me how you workaround this.

Regards,
Wincent_Altera