- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello,
Anyone know what i may be doing wrong or need to do in order to get past this simulation problem? ** Error: C:/intelfpga/17.1/quartus/eda/sim_lib/mentor/twentynm_atoms_ncrypt.v(38): in protected region I get the above error in Mentor's Questasim. I have tried to compile my code base with both Revision 16.1 and 17.1. Both of them report the same error. I use Verilog netlist. Thank you. Best regards, SanjayLink Copied
2 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
This type of error may be because of compilation order.Can you elaborate on compilation steps or attach the transcript. Refer below link if may help https://www.altera.com/support/support-resources/knowledge-base/solutions/rd12162013_881.html Let me know if this has helped resolve the issue you are facing or if you need any further assistance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Thank you for helping. This is what I do -
1. Create a qsys system with the platform designer in Q17.1 or 16.1 targeting an Arria10GX device. 2. Create testbench for the system from the Tools menu in the qsys generator. 3. Go to the <component>_tb/sim/mentor in questasim version 10.7a 4. Run msim_setup.tcl. Which creates aliases dev_com, com and elab_debug. 5. I run dev_com, then com and then elab_debug. That’s when I get the error. It doesn’t seem to matter what I put in the qsys. For my test case I have a clock, reset and altera’s quad spi flash programmer ip. To me it seems like there is something wrong in the verilog version of the encrypted twentynm files. While the problem occurs during elab of twentynm_atoms_encrypt.v the encrypted hip file reports incorrect carriage return warning. It may or may not be related. Please help. Cannot go far in creating simulation env if intel provided ip blocks do not work. Thank you. Best regards
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page