Error: Can't fit design in device

[Altera_Forum]

Hello everybody, 

 I'm using the Stratix II Board with the Quartus II 6.0 software. My first design went very well (building, compiling, running), but when I tried to add the EPCS-Controller to that design and started to compile, the following error message appeared:  ++++++++++++++++++++++ Start Error Message ++++++++++++++++++ Error: Can't use active serial memory interface block -- configuration scheme is not Active Serial Error: Can't fit design in device Error: Quartus II Fitter was unsuccessful. 2 errors, 1 warning  Error: Processing ended: Thu Nov 27 15:12:38 2008  Error: Elapsed time: 00:00:05 Error: Quartus II Full Compilation was unsuccessful. 2 errors, 169 warnings +++++++++++++++++++++++ End Error Message ++++++++++++++++++  The error points to a comment line in the epcs_controller.vhd, provided by altera.   On my research in the internet I found this error message in context with the DDR2-Controller ( http://www.altera.com/support/kdb/solutions/rd02132007_26.html ). Does anyone know if this is the same error and can be solved by the same way? I didn't try to install the patch yet due to both, I don't want to bug the system administrator because of something which doesn't work (worst case) and I didn't find the spezific patch yet.   I'd be very grateful if someone knows any advice.  Thanks in advance! Cheers,  Stahlkopf

[Altera_Forum]

Go to Quartus II menu: 

 Assignment -> Settings -> Device -> Device and Pin Options  then choose the configuration tab and select "Active Serial".  Cheers OD

[Altera_Forum]

Hello OrchestraDirector, 

 Thanks alot! Everything worked fine and I feel kind of stupid right now ;)   But now I do have another problem:  I compiled the hardware successfully and programmed it into my FPGA. But the IDE tells me there wouldn't be enough space to store my files. First, I thought there isn't enough space onchip - that's why I implemented the EPCS-Controller - but now it seems like this was not the problem.   This is the Error-Report: +++++++++++++++++++++++ Start Error Messege +++++++++++++++++ Compiling simple_socket_server.c... Linking simple_socket_server_0.elf... /cygdrive/c/Programme/altera/kits/nios2_60/bin/nios2-gnutools/H-i686-pc-cygwin/bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld: region epcs_controller is full (simple_socket_server_0.elf section .text). Region needs to be 197792 bytes larger. /cygdrive/c/Programme/altera/kits/nios2_60/bin/nios2-gnutools/H-i686-pc-cygwin/bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld: region epcs_controller is full (simple_socket_server_0.elf section .rodata). Region needs to be 12404 bytes larger. /cygdrive/c/Programme/altera/kits/nios2_60/bin/nios2-gnutools/H-i686-pc-cygwin/bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld: region onchip_memory_0 is full (simple_socket_server_0.elf section .bss). Region needs to be 174124 bytes larger. /cygdrive/c/Programme/altera/kits/nios2_60/bin/nios2-gnutools/H-i686-pc-cygwin/bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld: section .rodata [00021000 -> 00024873] overlaps section .text [00021000 -> 00051c9f] /cygdrive/c/Programme/altera/kits/nios2_60/bin/nios2-gnutools/H-i686-pc-cygwin/bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld: section .bss [00001e04 -> 0004282b] overlaps section .text [00021000 -> 00051c9f] collect2: ld returned 1 exit status make: *** [simple_socket_server_0.elf] Error 1 Build completed ++++++++++++++++++++++++ End Error Message +++++++++++++++++  As you can see, I'm just trying to run a standard program from ALTERA with my hardware. So it's probably just a problem with the settings again. In the System-Library properties I set the (.text) and (.rodata) to the epcs_controller hoping the program code would be stored in the EPCS-Controller flash memory.  Do you know if I did anything wrong? Or if it's 'just' a problem with the settings again?   Thanks again so far!!! And thanks again in advance for all your help :)   Cheers, Stahlkopf

[Altera_Forum]

How big is your program? How much on-chip memory is there? Have you enough to run the program. 

 I'm sure someone will correct me if I'm wrong but I'm pretty sure you can't run the program out of the EPCS device - you have to load it into RAM. That might explain the error message relating to the on-chip memory as for the epcs controller messages, other than checking the amount of spare room in your EPCS I can't think.

[Altera_Forum]

Hello batfink, 

 thank you for your reply.  The on-chip memory is 96kbytes at the moment. But where can I see how much RAM my current configuration requires?  Obviously I understood something wrong, hopefully you can help me to fix that. Why do I need the RAM at this moment? I was just compiling the program in the IDE, when I got this error report. I thought I'd just compile the program on my computer and afterwards load it into my design (when I press the button "Run As -> Nios II Hardware"). Furthermore I thought I'm going to load the program into a flash memory (in this case the memory of the EPCS-Controller), not into a RAM-Memory.  Is there a way to avoid an external RAM and just run on the on-chip RAM? I'll probably get a decent problem when I try to route an external RAM on my circuit board, too.   Thanks for your help. Cheers,  Stahlkopf

[Altera_Forum]

Only point your reset address (in SOPC Builder) at the EPCS controller. Point the rest of your memory sections at other (volatile) memory. The EPCS (like other SPI devices) cannot be used (easily or directly) to run code. 

   --- Quote Start ---  /cygdrive/c/Programme/altera/kits/nios2_60/bin/nios2-gnutools/H-i686-pc-cygwin/bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld: region epcs_controller is full (simple_socket_server_0.elf section .text). Region needs to be 197792 bytes larger. /cygdrive/c/Programme/altera/kits/nios2_60/bin/nios2-gnutools/H-i686-pc-cygwin/bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld: region epcs_controller is full (simple_socket_server_0.elf section .rodata). Region needs to be 12404 bytes larger. /cygdrive/c/Programme/altera/kits/nios2_60/bin/nios2-gnutools/H-i686-pc-cygwin/bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld: region onchip_memory_0 is full (simple_socket_server_0.elf section .bss). Region needs to be 174124 bytes larger. /cygdrive/c/Programme/altera/kits/nios2_60/bin/nios2-gnutools/H-i686-pc-cygwin/bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld: section .rodata [00021000 -> 00024873] overlaps section .text [00021000 -> 00051c9f] /cygdrive/c/Programme/altera/kits/nios2_60/bin/nios2-gnutools/H-i686-pc-cygwin/bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld: section .bss [00001e04 -> 0004282b] overlaps section .text [00021000 -> 00051c9f] collect2: ld returned 1 exit status  --- Quote End ---    The above snippet tells you how much memory you need...and there's no way you're going to fit it in onchip memory. In an example that I just compiled, Simple Socket Server required:   text data bss dec hex filename 265088 8692 42496 316276 4d374 simple_socket_server.elf  Cheers,  - Ura

[Altera_Forum]

Hello Ura, 

 thank you for your reply. I added an external RAM to my design. But to keep my project interesting, I got a new error ;-)   When I try to compile the hardware in Quartus, an error messege appears:   +++++++++++++++++++++++Start Error Messege++++++++++++++++++ Error (10481): VHDL Use Clause error at ddr_sdram_auk_ddr_sdram.vhd(22): design library "auk_ddr_lib" does not contain primary unit "auk_ddr_functions" Error: Node instance "ddr_sdram_auk_ddr_sdram_inst" instantiates undefined entity "ddr_sdram_auk_ddr_sdram" Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 10 warnings Error: Processing ended: Wed Dec 03 11:58:24 2008 Error: Elapsed time: 00:00:21 Error: Analysis and Elaboration failed. The constraints script will not be able to add any constraints. Error: Tcl error: ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last. while executing "error $result" (procedure "check_paths" line 13) invoked from within "check_paths $wrapper_name $do_analysis" invoked from within "if { $run_var != 0 } {# ########################################################################### Procedure check_paths() will analyse the project..." (file "./add_constraints_for_ddr_sdram.tcl" line 75) invoked from within "source ./add_constraints_for_ddr_sdram.tcl" (file "auto_add_ddr_constraints.tcl" line 11) Error: Evaluation of Tcl script auto_add_ddr_constraints.tcl unsuccessful Error: Quartus II Shell was unsuccessful. 8 errors, 10 warnings Error: Processing ended: Wed Dec 03 11:58:26 2008 Error: Elapsed time: 00:00:24 Error: Quartus II Full Compilation was unsuccessful. 8 errors, 10 warnings +++++++++++++++++++++End Error Messege+++++++++++++++++++++++   The error points to a file called ddr_sdram_0_auk_ddr_sdram.vhd (my RAM is called ddr_sdram_0 in the SOPC Builder) in which the library auk_ddr_lib is included. I searched my hole hard disk for this library without any success. Furthermore I was searching in the internet for this file but I just found some pages with Asian characters (which I unfortunatelly can't read) and an Altera manual for the "PCI High-Speed Development Kit, Stratix Professional Edition", which didn't help here.    I'm just very confuesed, because the standard design worked very well with this RAM configuration. But how can it working without the file? Does anyone know if I need to download something to get it working?    Thanks for your help!!! Cheers,   Stahlkopf