Error: DDR timing cannot be verified until project has been successfully compiled.

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Error: DDR timing cannot be verified until project has been successfully compiled.

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Hello

I have a project with 2 DDR2 created with DDR2 SDRAM Controller v.13 and while compiling I have an error:

error: ddr timing cannot be verified until project has been successfully compiled.

I have found the solution:

"workaround

regenerate your controller in ip toolbench and recompile the project. the

timing analysis script now completes correctly."

I have regenerated my controller using IP Toolbench but it didn't helped.

I use Quartus II 13.0 on Linux 2.6.18.el5 (Cent OS)

Please help

Best Regards

Agata

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