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Altera_Forum
Honored Contributor I
1,405 Views

Error during generating simulation code in Qsys

I am using Quartus lite 16.1 on Ubuntu 16.10. I have a design that I can synthesize and can run on DE1-SoC board, and I am trying to do some simulation with my design.  

I am trying to generate testbench system by Generate -> Generate testbench system. I chose the simulation model to be verilog, and I wanted to create testbench qsys system as "Simple, BFMs for clocks and resets". However during generation, sys_pll is crashing. The log file seems to be not related to my design, and is related to the tool. Here is the log. Can I get some insights on how to fix this? The full log is in the attachment. 

 

Error: sys_pll: Execution of script /tmp/alt7312_8544295832717336619.dir/0030_sys_pll_gen/proj.tcl failed 

Error: sys_pll: Info: ******************************************************************* 

Error: sys_pll: Info: Running Quartus Prime Shell 

Error: sys_pll: Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition 

Error: sys_pll: Info: Copyright (C) 2016 Intel Corporation. All rights reserved. 

Error: sys_pll: Info: Your use of Intel Corporation's design tools, logic functions 

Error: sys_pll: Info: and other software and tools, and its AMPP partner logic 

Error: sys_pll: Info: functions, and any output files from any of the foregoing 

Error: sys_pll: Info: (including device programming or simulation files), and any 

Error: sys_pll: Info: associated documentation or information are expressly subject 

Error: sys_pll: Info: to the terms and conditions of the Intel Program License 

Error: sys_pll: Info: Subscription Agreement, the Intel Quartus Prime License Agreement, 

Error: sys_pll: Info: the Intel MegaCore Function License Agreement, or other 

Error: sys_pll: Info: applicable license agreement, including, without limitation, 

Error: sys_pll: Info: that your use is for the sole purpose of programming logic 

Error: sys_pll: Info: devices manufactured by Intel and sold by Intel or its 

Error: sys_pll: Info: authorized distributors. Please refer to the applicable 

Error: sys_pll: Info: agreement for further details. 

Error: sys_pll: Info: Processing started: Fri May 26 16:18:42 2017 

Error: sys_pll: Info: Command: quartus_sh -t /tmp/alt7312_8544295832717336619.dir/0030_sys_pll_gen/proj.tcl 

Error: sys_pll: Info (23030): Evaluation of Tcl script /tmp/alt7312_8544295832717336619.dir/0030_sys_pll_gen/proj.tcl was successful 

Error: sys_pll: Info: Quartus Prime Shell was successful. 0 errors, 0 warnings 

Error: sys_pll: Info: Peak virtual memory: 773 megabytes 

Error: sys_pll: Info: Processing ended: Fri May 26 16:18:43 2017 

Error: sys_pll: Info: Elapsed time: 00:00:01 

Error: sys_pll: Info: Total CPU time (on all processors): 00:00:00 

Error: sys_pll: Inconsistency detected by ld.so: dl-close.c: 762: _dl_close: Assertion `map->l_init_called' failed! 

Error: sys_pll: Execution of script run_simgen_cmd.tcl failed 

Error: sys_pll: Info: ******************************************************************* 

Error: sys_pll: Info: Running Quartus Prime Shell 

Error: sys_pll: Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition 

Error: sys_pll: Info: Copyright (C) 2016 Intel Corporation. All rights reserved. 

Error: sys_pll: Info: Your use of Intel Corporation's design tools, logic functions 

Error: sys_pll: Info: and other software and tools, and its AMPP partner logic 

Error: sys_pll: Info: functions, and any output files from any of the foregoing 

Error: sys_pll: Info: (including device programming or simulation files), and any 

Error: sys_pll: Info: associated documentation or information are expressly subject 

Error: sys_pll: Info: to the terms and conditions of the Intel Program License 

Error: sys_pll: Info: Subscription Agreement, the Intel Quartus Prime License Agreement, 

Error: sys_pll: Info: the Intel MegaCore Function License Agreement, or other 

Error: sys_pll: Info: applicable license agreement, including, without limitation, 

Error: sys_pll: Info: that your use is for the sole purpose of programming logic 

Error: sys_pll: Info: devices manufactured by Intel and sold by Intel or its 

Error: sys_pll: Info: authorized distributors. Please refer to the applicable 

Error: sys_pll: Info: agreement for further details. 

Error: sys_pll: Info: Processing started: Fri May 26 16:18:43 2017 

Error: sys_pll: Info: Command: quartus_sh -t run_simgen_cmd.tcl 

Error: sys_pll: Info: ******************************************************************* 

Error: sys_pll: Info: Running Quartus Prime Analysis & Synthesis 

Error: sys_pll: Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition 

Error: sys_pll: Info: Copyright (C) 2016 Intel Corporation. All rights reserved. 

Error: sys_pll: Info: Your use of Intel Corporation's design tools, logic functions 

Error: sys_pll: Info: and other software and tools, and its AMPP partner logic 

Error: sys_pll: Info: functions, and any output files from any of the foregoing 

Error: sys_pll: Info: (including device programming or simulation files), and any 

Error: sys_pll: Info: associated documentation or information are expressly subject 

Error: sys_pll: Info: to the terms and conditions of the Intel Program License 

Error: sys_pll: Info: Subscription Agreement, the Intel Quartus Prime License Agreement, 

Error: sys_pll: Info: the Intel MegaCore Function License Agreement, or other 

Error: sys_pll: Info: applicable license agreement, including, without limitation, 

Error: sys_pll: Info: that your use is for the sole purpose of programming logic 

Error: sys_pll: Info: devices manufactured by Intel and sold by Intel or its 

Error: sys_pll: Info: authorized distributors. Please refer to the applicable 

Error: sys_pll: Info: agreement for further details. 

Error: sys_pll: Info: Processing started: Fri May 26 16:18:45 2017 

Error: sys_pll: Info: Command: quartus_map Computer_System_System_PLL_sys_pll.qpf --simgen --ini=disable_check_quartus_compatibility_qsys_only=on --simgen_parameter=CBX_HDL_LANGUAGE=VERILOG 

.......................................... 

.......................................... 

.......................................... 

Error: sys_pll: Info: Total CPU time (on all processors): 00:00:36 

Error: sys_pll: Inconsistency detected by ld.so: dl-close.c: 762: _dl_close: Assertion `map->l_init_called' failed! 

Error: Generation stopped, 209 or more modules remaining 

Error: qsys-generate failed with exit code 1: 155 Errors, 20 Warnings 

Error: There were errors creating the testbench system.
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3 Replies
Altera_Forum
Honored Contributor I
50 Views

Just to make sure: you've exported the PLL input reference clock from the system, correct? This is necessary for Qsys to automatically add the clock BFM when generating the testbench system.

Altera_Forum
Honored Contributor I
50 Views

I have the similar problem when generating the Altera PLL 16.1 wrapper... And I'm not using Qsys. 

Is it a bug of version 16.1?
Altera_Forum
Honored Contributor I
50 Views

Just tried with 15.1 ... Simgen runs successfully. Cheers! 

 

--- Quote Start ---  

I have the similar problem when generating the Altera PLL 16.1 wrapper... And I'm not using Qsys. 

Is it a bug of version 16.1? 

--- Quote End ---  

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