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Error in placing the HPS DDR4 EMIF



I am using Quartus 21.2.0 Build 72 06/14/2021 SC Pro Edition software with COMXpress Stratix® 10 SoC SoM (


I have problem with the fitting HPS DDR4 EMIF to the device, error message is here:

Error(12934): Fitter was unable to place an EMIF/PHYLite system
Info(13138): Please try constraining some of the following signals to pin locations or IO banks
Info(13139): ddr4_3_mem_dqs[0]
Info(13139): ddr4_3_mem_dqs_n[0]
Info(13139): ddr4_3_mem_dqs[1]
Info(13139): ddr4_3_mem_dqs_n[1]
Info(13139): ddr4_3_mem_dqs[2]
Info(13139): ddr4_3_mem_dqs_n[2]
Info(13139): ddr4_3_mem_dqs[3]
Info(13139): ddr4_3_mem_dqs_n[3]
Info(13139): ddr4_3_mem_dqs[4]
Info(13139): ddr4_3_mem_dqs_n[4]
Info(13139): ddr4_3_mem_dqs[5]
Info(13139): ddr4_3_mem_dqs_n[5]
Info(13139): ddr4_3_mem_dqs[6]
Info(13139): ddr4_3_mem_dqs_n[6]
Info(13139): ddr4_3_mem_dqs[7]
Info(13139): ddr4_3_mem_dqs_n[7]
Info(13139): ddr4_3_mem_ck[0]
Info(13139): ddr4_3_pll_ref_clk
Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IO_LANE(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at and search for this specific error message number.
Error(175001): The Fitter cannot place 1 IO_LANE, which is within External Memory Interfaces for HPS Intel Stratix 10 FPGA IP soc_system_emif_s10_hps_2_altera_emif_s10_hps_1924_ew73tti.
Info(14596): Information about the failing component(s):
Info(175028): The IO_LANE name(s): soc_system_i|emif_s10_hps|emif_s10_hps_2|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[0].lane_inst|lane_inst
Error(16234): No legal location could be found out of 4 considered location(s). Reasons why each location could not be used are summarized below:
Error(175005): Could not find a location with: HPS_AC_TILE_RESERVATION_ID of HPS_LANE (4 locations affected)
Info(175029): IO12LANE_X52_Y361_N0
Info(175029): IO12LANE_X52_Y362_N1
Info(175029): IO12LANE_X52_Y363_N2
Info(175029): IO12LANE_X52_Y364_N3
Error(15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.
Error(16297): An error has occurred while trying to initialize the plan stage.
Error: Quartus Prime Fitter was unsuccessful. 7 errors, 8 warnings
Error: Peak virtual memory: 16552 megabytes
Error: Processing ended: Fri Oct 29 17:30:30 2021
Error: Elapsed time: 00:07:13
Error: System process ID: 15268
Error(293001): Quartus Prime Fitter was unsuccessful. 9 errors, 8 warnings


This not lead me to some idea where canbe a problem so I asking here....


Here is some prehistory:

I take make hps system with DDR4 sdram controller based on the Reflexcies reference design and pin constraints and it fitted without problem.

After that I add other DDR4 controllers with exaple designs also from Reflexciesa (3 more DDR4 controllers) and some other logics also with top level io.

Here this type error arise.

Trying to identify the problem I remove the pins which corresponds to banks 2L, 2M, 2N,  where is DDR4 controllers pins resides but the problem persist (So now only the HPS DDR4 pins are in this banks).

Can someone try to help me?

Thank you and best regards!








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2 Replies
Honored Contributor III

The easiest thing to do would be to use the Interface Planner tool in Quartus to find legal locations for your additional external memory interfaces.  That way you can guarantee that the I/O and resources needed for the additional interfaces are available.


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Problem justified - in 64 bits EMIF configuration it is not possible to use pins in banks 2L, 2M, 2N in other purposes than DDR4

Anyway thanks for answer

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