Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Error:op has outgoing edge with wrong producer!

Altera_Forum
Honored Contributor II
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I am getting these type of error while generating the HDL using Qsys 

 

Error: /dvtools/dvtools/altera/quartus14.1/ip/altera/fir_filter_2d/lib/vip_packet_reader.hpp:150:48: op has outgoing edge with wrong producer! (op_10122:@array_assign) 

Error: /dvtools/dvtools/altera/quartus14.1/ip/altera/fir_filter_2d/lib/vip_packet_reader.hpp:156:85: op has outgoing edge with wrong producer! (op_10150:writeDataAndEop) 

 

 

PLease tell me the reason for this as i am not able to find out the reason for this.
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Altera_Forum
Honored Contributor II
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Did you figure out what the issue was? I am getting similar failure intermittently during Qsys HDL generation. 

 

Thanks.
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