The attached screenshots show errors received when trying to import HDL to create an AXI4Lite slave Generic Component in Platform Designer. Following the Intel Video for "Importing HDL to create Qsys Pro Components", the process seemed applicable even though the example from the video pertained to an Avalon MM slave component. So, after separating the imported signals into conduit, clock sink, and reset sink I received 3 errors shown in the first screenshot mentioning that a clock and reset interface must be assigned to the axi4l interface. After assigning the clock sink and reset sink in the parameter of the axi4l interface, I received 5 errors. It appears I am fundamentally missing an aspect of this feature. Any thoughts? Thanks, Roy
You have to set the associated clock and reset using the pop-up lists at the top of the parameters there. It still says "none" in both screenshots.
Must be a bug in the tool because as shown in the second screenshot, the parameters were assigned using the drop down menu but the drop menu returns to none while the parameters tab shows they are assigned. Screenshot two is the result of using the drop down menu.
Hmmm, very strange. I just created a new generic component and tried the AXI4 slave template to fill in the interfaces and did not see this issue. Do the pop-ups jump back to "none" every time you try to select associated clock and reset?
Maybe try removing and then adding back your HDL design file(s).
From the error message there, the altera_axi4lite_slave interface must have clock and reset interface associated. I see "none" in the boxes. Simply click and select clock_sink and reset_sink for associated clock and associated reset respectively. Once you select, the parameter window automatically update it and then should be error free.
I should also mention that this is the Linux version of Quartus Prime Pro. It does not seem to keep the selection in the drop down menu although it assigns the selection to the parameter option as shown.