Error when generating JESD204B Design EXample

[Altera_Forum]

Hi all, 

  I'm new on using Intel JESD204B IP Core, and Quartus II version I've tried is 16.1, 17.0 and 17.1.   Since it's my first time trying to implementing the JESD204B IP-Core, I'm directly follow the Intel FPGA JESD204B Design Example step-by-step. But I couldn't get the desired output files as the user guide instructs. **Link of user guide: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug-dex-a10-jesd204b.pdf   According to page 4 of user guide, the output file structure should be something like attached pic_1.   However, when I click the "Generate Example Design" button with preset configuration in IP Parameter Editor Pro, multi errors occurred (pic_2). The message said 'cannot run program "sys-script" (in driver\qii installed_path\version\ip\a;tera\altera_jesd204b\src\top)'.  I've tried with QuartsII Prime Pro(30-Days Trial Version) 16.1,17.0 and 17.1. All of these versions having the same error messages and I can't have completed designed example shown as user guide.   And of course, I tried to re-installed all these three versions but have no luck.  Did I miss anything or there's other plug/patch I could install?  Thanks in advance!!!