Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Example for constraining Source Synchronous Interfaces in TimeQuest

Altera_Forum
Honored Contributor II
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Attached is a design that fully constrains a source synchronous interface using the TimeQuest timing analyzer. 

 

simply recompile the design, launch TimeQuest then run the script "Report_SS_Tester.tcl" to view results.
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Altera_Forum
Honored Contributor II
539 Views

Did you know there is a free online training on this topic? 

Constraining and Analyzing Timing for Source Synchronous Circuits with TimeQuest 

http://www.altera.com/training/timequest-source-synchronous
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