Example of a simple Custom IP interface using platform designer similar to interface to user logic component.

[JClar]

I wish to create an interface between NIOS as an (avalon register slave) and an external chip that requires a chipselect_n, read_n line, write_n line, 8 data bits.

Many years ago we used SOPC custom component called interface to user logic. It worked well and was easy to use.

Is there anything like that currently supported in Intel platform designer?

Most examples are too complex for what we need.

[AnandRaj_S_Intel]

Hi,

You can refer the attachment for example. Also from below link you can find the memory map template.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-avalon-mm.html?_ga=2.157854394.1605983552.1543195159-1502858605.1541574908&erpm_id=6176508

Custom component creation.

https://www.youtube.com/watch?v=v6rhbVABlo8

Regards

Anand

[JClar]

Anand,

Thank-you for your answer. It is helpful to describe the basic tools to create a project but that was not the question I asked.

Let me try again.

I need to create a custom IP that will give me a CS_n signal, Rd, Wr, and data bus signals using platform designer custom IP tool. I assume using a conduit interface.

Is there a document that describes the signals & interface tab? It states <add signal> and an asterisk. (*).

I assume the names are writeline, readline, etc. Where is a description of these signals and how do I select the correct name?

Jack

[sstrell]

It sounds like you're trying to access an external tristate bus. You can use the generic tri-state controller and Avalon to tri-state bridge components to access it. The Nios would be the master, not the slave. You don't need a custom component to do this.