I've implemented a DMA controller in Qsys with the read master port exported, and the write master port connected to PCIe. The DMA is configured for burst xfers. I'm looking at the exported signals (read master port) in signaltap.
When I initiate a burst xfer from the host over PCIe, the dma controller initiates one read, but only one read. I've tried both holding 'read_data_valid' high and toggling it (by inverting 'read_n' and connecting to 'read_data_valid'). 'wait_request' is held low (invalid). After the initial read pulse, the dma is inactive for at least 300 usec. I can write/read the DMA control/status registers and they have correct values, and the DMA does start properly on command.
I don't know what could be hanging the DMA, and can't believe it's really so slow as to have hundreds of usec between reads.
