Exporting an Avalon - MM bus that connects 2 QSYS components.

[SKon1]

Hello,

Inside QSYS I have 2 components interconnected via Avalon MM:

Component A is an Avalon MM master.

Component B is an Avalon MM slave.

I want to export the Avalon bus signals out of QSYS and connect it to Component C which is written in HDL (Component C will only monitor the signals).

A straightforward solution would be to manually edit the QSYS wrapper and add the signals of interest as ports to the wrapper.

But is there a "native" way to do it ?

[Kenny_Tan]

You mention the correct way, after click on the export button in the qsys. You can use the wrapper to connect out those port to your component C.

[SKon1]

This won't work.

Once I export I cannot connect it in QSYS.

[Kenny_Tan]

what are the specific signal that you want to monitor? I would suggest you use signal tap to monitor it.

[sstrell]

The easiest way to use an interface both inside and outside a Platform Designer system is to use a pipeline bridge component added to your system design. It has a master interface on one side and a slave interface on the other. Connect one side or the other to components A or B and then export the other side. You can configure the bridge to act as "just wires" or as a true pipeline register, which can help with timing.

#iwork4intel

[SKon1]

Hi sstrell,

I thought about it - but this also won't work.

I'll explain again what I want to do:

I want to connect component A (master) to component B (slave) which is inside QSYS and export the same bus outside of QSYS to component C (also slave).

Component C is written in RTL and does some monitoring on the address space of the Avalon Bus. It's completely passive and doesn't return any data to component A.

The problem with your suggested approach is that QSYS doesn't allow 2 Avalon MM slaves to share overlapping address spaces.

[sstrell]

So are you saying that C is basically monitoring what's going on between A and B and you want C to see the addressing being done by A? If B is a custom component, I think the easiest thing to do would be to add outputs from B and export them as a conduit, which I think is what you suggested originally.

#iwork4intel

[SKon1]

Yes sstrell. Your understanding is correct.

Only B isn't a custom component so I don't have access to it.

Seems like QSYS doesn't allow exporting just ANY signal of interest.

This leaves me only one choice - which is manually editing the wrapper...

Extremely annoying.

[sstrell]

OK, if B is not custom, then I'd break this into two .qsys files, one for A and one for B. Export A's master interface from its .qsys and export B's slave interface from its .qsys, connect them together and to C in RTL outside of Platform Designer.

#iwork4intel