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TFPGA
Beginner
1,570 Views

External memory Interface Intel Cyclone 10 FPGA IP configure DATA bus size from Avalon MM interface

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I am migrating a system from an old Arria II to a Cyclone 10 GX, so I need to migrate from a DDR2 interface connected to a Avalon MM with an interface of 128 bits.

 

I would like to use this controller in the Cylone 10 GX Development Kit, so I instanciate the component into my system and I use the Template "Cyclone 10 GX FPGA Development Kit with DDR3" for the Memory parameters.

 

After that it creates a Avalon MM interface to write/read into the Memory of 320 bits that it is not compatible with a standard Avalon Memory Map Clock Crossing bridge interface (multiple of 2) that my system uses to write and read data.

 

If I open the example from Altera for this memory the parameters are exactly the same but the Avalon MM interface has 256 bits, so it can be use.

 

How I can modify this Avalon Interface to be 256 or 128?

 

Thanks.

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1 Solution
NurAida_A_Intel
Employee
116 Views

Hi ADona,

Cyclone 10 GX package only support DDR3 x40 with ECC. This information cover in “Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook” page 166.

 

info.PNG

So, you need to turn on the “Enable Error Detection and Correction Logic with ECC” under the “Controller” setting in order to use DDR3 x40.

Option1.PNG

Another option is you can use 32 DQ width and you can see now the amm interface become 256bits.

Option2.PNG

Hope this helps.

Thanks

Regards,

NAli1

View solution in original post

4 Replies
NurAida_A_Intel
Employee
116 Views

Hi ADona,

 

The Avalon MM interface setting is actually depend on the DQ width setting and the clock rate of user logic set by user. To get better clue on how to get the Avalon interface setting, please refer to below examples. Assuming the DQ width is equal to 64.

Example 1:

 DQ width = 64

Clock rate of user logic = Half

Avalon MM interface = DQ width x Clock rate of user logic

                                       = 64 x 2 = 128 bits

Example 2:

DQ width = 64

Clock rate of user logic = Quarter

Avalon MM interface      = DQ width x Clock rate of user logic

                                            = 64 x 4 = 256 bits

I sincerely hope this helps.

 

Thanks

Regards,

NAli1

TFPGA
Beginner
116 Views

Thanks Nali1,

 

The problem is that my DQ is 40, and this data cant be modified because the external memory has a dataline of 40 bits (Cyclone 10 GX FPGA Development Kit).

 

And the Avalon bridge only accept multiple of 2 data witdh.

 

Error: core.ddr3.ctrl_amm_0: Data width must be of power of two and between 8 and 4096

 

Regards,

ADona

 

 

 

NurAida_A_Intel
Employee
117 Views

Hi ADona,

Cyclone 10 GX package only support DDR3 x40 with ECC. This information cover in “Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook” page 166.

 

info.PNG

So, you need to turn on the “Enable Error Detection and Correction Logic with ECC” under the “Controller” setting in order to use DDR3 x40.

Option1.PNG

Another option is you can use 32 DQ width and you can see now the amm interface become 256bits.

Option2.PNG

Hope this helps.

Thanks

Regards,

NAli1

View solution in original post

TFPGA
Beginner
116 Views

Thanks, that works.

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