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Honored Contributor I
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FIFO based on DDR

Hi All. 

Did any body try to implement FIFO based on DDR (using Altera's DDR controller) ? 

 

Thanks
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Honored Contributor I
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I started looking into this a few years ago (application required full memory bandwidth at DDR), and I came to the conclusion that it likely would not be possible, due to the extra overhead associated with interfacing DDR parts. In your case, you would have to determine what sort of requirements you have, and then take a look at the actual memory bandwidth of a DDR interface, and make that decision. At the time, I found that Altera's documentation was pretty nebulous with respect to performance (for their supplied DDR interface logic). That might have changed, so I don't know. I was hoping that they would have some sort of equation stating mem_bandwidth = f(ratio_writes, ratio_reads, clock_rate), or something to that effect. Instead, there were 3-4 example designs, with what appeared to be the empirically-determined efficiency. 

 

In my case, we had put a DDR memory on the board for the purpose of a delay FIFO (start writing, t_delay, start reading => delays data for duration of t_delay, indefinitely). I needed to run at 2x clock rate (which is why we went with DDR), but then found out, after the fact, that the memory bandwidth was really only 60% or so of 2x clock rate. So, we went about it a different way. 

 

You might have a lot better luck if your application is something like a rate-adapter with a burst on one side and constant reading @ rate on the other. Hope this helps.
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Honored Contributor I
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It can be done. I can't share any code because it's proprietary but yes you can do a fifo. I suggest putting small dc fifo's on the data in and data out ports of your fifo code to handle ddr's bursty nature (when you want max throughput) and if you need to transfer clock domains. Also, look at some single clock fifo examples on the web to get ideas on implementing the controlling state machine.

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Honored Contributor I
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In the simpliest form if you made a logic block that turned a single port memory interface into a dual port interface, then you could just hook the ddr up to one side, then use the standard fifo logic from somewhere say opencores.org to interface with the dual port side. I think specific applications may bring about performance advantages, if say you can deal with a packet basis.  

 

Another thought, what if you used the SOPC builder and did a little mix matching of parts? Don't really know specfically, but you may be able to make something work there although it probably will not be the fastest. 

 

Just tossing out ideas. 

 

kevin
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