FIFO output delay by one clock cycle

Intel® Quartus® Prime Software

Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

FIFO output delay by one clock cycle

395 Views

Hi sir/madam.

I am working on FIFO memory in max10 device my problem is when i read data from FIFO output is coming zero by one clock cycle.

My task is to send data from FIFO to USB. The depth of FIFO is 32 and 12 bit wide when i read data from 1st FIFO after 2nd FIFO output is coming zeros for one clock cycle for all FIFO how to handle with this problem can i get any help for this.

Thanks in advance.

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.