Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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FIFO output delay by one clock cycle

m_kumar
New Contributor I
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Hi sir/madam.

I am working on FIFO memory in max10 device my problem is when i read data from  FIFO output is coming zero by one clock cycle. 

My task is to send data from FIFO to USB. The depth of FIFO is 32 and 12 bit wide when i read data from 1st FIFO after  2nd FIFO output is coming zeros for one clock cycle for all FIFO how to handle with this problem can i get any help for this.

Thanks in advance.

 

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