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RMees
Novice
834 Views

FPGA IP Evaluation Mode when using a remote JTAG server.

My design contains a SerialLite III IP, but I dont have the required license.

The FPGA image that is produced is a "time_limited" version.

I run my FPGA tools on a cloud based Linux machine.

The FPGA board is on a different machine located in the cloud.

My local FPGA tools access the FPGA board using a remote JTAG server that runs on the system that has the FPGA board installed.

According to  AN 320: Using Intel® FPGA IP Evaluation Mode there is a Tethered and a Untethered mode.

 

When I use a remote JTAG server to load the FPGA board, is this the Tethered or Untethered mode?

 

If this is Untethered, can I move the .ocp file to the remote server to convert the situation into a Tethered mode? If soo, where should I move the file to.

 

Probes show that the link_up signals are not going active.

This behaviour matches what the user guide says would happen.

"The Intel Quartus Prime software uses Intel FPGA IP Evaluation Mode Files (.ocp) in your project directory to identify your use of the Intel FPGA IP Evaluation Mode evaluation program. After you activate the feature, do not delete these files.

When the evaluation time expires, the link_up signal goes low." 

 

 

 

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5 Replies
Nooraini_Y_Intel
Employee
52 Views

Hi,

 

Currently I am reviewing the forum for any open questions and found this thread. I apologize that no one seems to answer this question that you posted. Since it has been a while you posted this question, I'm wondering if you have found the answer? If not, please let me know, I will try to assign/find someone to assist you. Thank you.

 

Regards,

Nooraini

 

RMees
Novice
52 Views

This is still an open question.

Nooraini_Y_Intel
Employee
52 Views

Hi RMees,

 

Apologize for long delay as I'm still finding the right engineer here that can help on this Serial Lite III Evaluation IP mode. As far I manage to test a simple time_limited .sof file using a different Evaluation IP from a remote host which indicate that when using remote JTAG server to load the FPGA board is in Tethered mode. in the project design, the OCP time out signal was set to active_high. After programming the time_limited .sof file from a remote host/machine, the Quartus programmer will prompt a small window showing the remaining time before expire. When running the SingnalTap I can observe the OCP ip_timeout singal is low which indicate the Evaluation IP has not yet expire.

 

Regards,

Nooraini

Nooraini_Y_Intel
Employee
52 Views

Hi RMees,

 

Do you still any question on this? In general as I tested before with a time_limited .sof (different Evaluation IP) using remote JTAG server to load the FPGA board this should be in Tethered mode.

 

Regards,

Nooraini

RMees
Novice
52 Views

I moved on and used a different design.

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