Hi! I'm relatively new in the world of FPGA programming. I wish to know a way to debug my circuit impleneted in an Altera FPGA. I heard about the following techique: implement the test hardware, the nios 2 processor and a uart. In this way I could communicate via pc to the nios 2 in order to set the inputs to my circuit and evaluate the outputs. Is this a usefull technique to debug my hardware? Where I can find documentations about this procedure? Or there exist a more easy way to debug my circuit in the FPGA?
Thanks in advice for the answer.
There are many built-in tools in Quartus that are simpler for debugging than the setup you've proposed. See the Quartus user guides and the Debug Tools user guide in particular (Lite/Standard or Pro depending on the edition of Quartus you're using). Signal Tap is probably the first thing you'll want to look at:
Not sure why you think you need to change code with ISSP other than instantiating the IP (unless you're saying that's the issue itself).
With Signal Tap, you don't have to change code, but you can't input values with it.
Can you provide more details on what you want/need?
Thank you for posting in Intel community forum, hope this message find you well and apologies for the delayed in response.
Based on the situation mention, as mentioned by sstrell, the signalTap/signalProbe seems to be an alternative for your case mention, more details to get you going can be found here.
Please do let us know if you have any clarification that we can help with.