I am trying to run the simulation and got this error. The "ast_sink_error' is one of the signal that I generated the IP from the library and I did check and it looks normally. The "ast_sink_error' is one the signal which has only 2 bit. I don't know where the 32-bit coming from.
Anyone had encounter on this error before and any resolution to this issue.
** Fatal: (vsim-3363) The array length (2) of VHDL port 'ast_sink_error' does not match the width (32) of its Verilog connection (5th connection).
Can you provide me the following information so I can better understand your problem:
- Can you upload the full error message you receive?
- Are you using FIR II IP?
- Which version of Quartus are you using?
We did not receive any response to the previous question that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.
PS: If you find any comment from the community or Intel Support to be helpful, feel free to give Kudos.