Fatal: (vsim-3807) Types do not match between component and entity for port "dataout".

[NSona1]

The error shown is-

The following is the error shown

** Fatal: (vsim-3807) Types do not match between component and entity for port "dataout".

#  Time: 0 ps Iteration: 0 Instance: /lineartau_1_vhd_vec_tst/i1 File: lineartau_1.vho Line: 86

# FATAL ERROR while loading design

# Error loading design

Error loading design

The code is-

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity lineartau_1 is

port (clk:IN std_logic;

dataout:OUT integer range -128 to 127);

end lineartau_1;

architecture arch_sine of lineartau_1 is

signal i:integer range 0 to 31:=0;

type memory_type is array (0 to 31) of integer range -128 to 127;

signal sin:memory_type:=(50,60,69,78,85,92,96,99,100,99,96,92,85,78,69,

60,50,40,31,22,15,8,4,1,0,1,4,8,15,22,31,40);

begin

process(clk)

begin

if rising_edge(clk)

then

dataout<=sin(i);

i<=i+1;

if(i=31)

then

i<=0;

end if;

end if;

end process;

end arch_sine;

The testbench created by Altera-Modelsim is-

LIBRARY ieee;                        

USE ieee.std_logic_1164.all;                 

ENTITY lineartau_1_vhd_vec_tst IS

END lineartau_1_vhd_vec_tst;

ARCHITECTURE lineartau_1_arch OF lineartau_1_vhd_vec_tst IS

-- constants                         

-- signals                          

SIGNAL clk : STD_LOGIC;

SIGNAL dataout : STD_LOGIC_VECTOR(7 DOWNTO 0);

COMPONENT lineartau_1

PORT (

clk : IN STD_LOGIC;

dataout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)

);

END COMPONENT;

BEGIN

i1 : lineartau_1

PORT MAP (

-- list connections between master ports and signals

clk => clk,

dataout => dataout

);

-- clk

t_prcs_clk: PROCESS

BEGIN

LOOP

clk <= '0';

WAIT FOR 500000 ps;

clk <= '1';

WAIT FOR 500000 ps;

IF (NOW >= 50000000 ps) THEN WAIT; END IF;

END LOOP;

END PROCESS t_prcs_clk;

END lineartau_1_arch;

I have defined dataout as an integer but still the testbench is defining it as a std_logic_vector.

Please help resolve this problem

[sstrell]

Where is the testbench coming from? Just edit it to change dataout to an integer type.

[Vicky1]

Hi,

Test bench is generated using "Start Test Bench Template Writer" and its template so in this case it needs to be edited like below,

SIGNAL dataout :  integer range -128 to 127; -- at signals

dataout : OUT integer range -128 to 127 --- at COMPONENT lineartau_1

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

[Vicky1]

Hi,

Are you able to do simulation?

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)