Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15551 Discussions

Feedback return path used by PLL(s) in location FRACTIONALPLL_X68_Y54_N0 is not of the recommended type

Lilian_61
New Contributor I
504 Views

I am using Cyclone V 5CGXFC FPGA. And there is 25MHz clock input. I used the 25MHz clock source to generate other frequency clock for platform usage. But when I use PLL, I got the below warning. I don't know how to resolve it.

 

Warning (12392): Feedback return path used by PLL(s) in location FRACTIONALPLL_X68_Y54_N0 is not of the recommended type

Info (177008): PLL pll_25MHz_cv:pll_25MHz_cv_inst|pll_25MHz_cv_0002:pll_25mhz_cv_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL

 

0 Kudos
7 Replies
SreekumarR_G_Intel
299 Views

Can I know what is the mode of the PLL used in the design ?

(ie Normal mode ; Zero Delay Buffer mode or No Compensation mode )

 

Would it possible to share the your setting and pin used for Inclk0 ?

 

Thank you,

 

Regards,

Sree

 

Lilian_61
New Contributor I
299 Views

The PLL used is Normal Mode.

Below is physical connection. The CLK25M_TXCO_FPGA1_AC_P/N is differential clock generated by TCXO.Screen Shot 2020-01-06 at 3.08.24 PM.png

In FPGA setting, the IO standard is set as DIFFERENTIAL LVPECL, and the CLK25M_TCXO_FPGA1_AC_P is the refclk of PLL module.

SreekumarR_G_Intel
299 Views

I created the small example design with Fractional PLL and the IO standrad specified . When I complie ,i got warning given below and which can be overiddern using below KDB link.

Warning (177007): PLL(s) placed in location &ltPLL location&gt do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/soluti...:

can you check the deign I attcahed and re-create the warning and post it back. This will help me analyze the further.

 

Thank you,

 

Regards,

Sree

Lilian_61
New Contributor I
299 Views

Thanks for your help.

I re-compile your project, and I don't find the same warning in report.

Screen Shot 2020-01-06 at 5.56.35 PM.png

The reason I want to resolve this warning, because there are timing analysis issue, and I think this warning have an effect.

I also post part of the other warnings here, may it can offer some help. I tried to fix it myself, but I failed.

The pll_clk50m, pll_clk25m, pll_clk62m5 and pll_clk20m are generated by PLL module.

---------------------------------------------------------------------------------------------------------------------------------

Warning (16305): Feedback path used by PLL(s) in location FRACTIONALPLL_X68_Y54_N0 was routed for regional clock compensation but the clock targeted for compensation was routed as a global clock

Warning (332174): Ignored filter at mi.sdc(37): pll_clk50m could not be matched with a port or pin or register or keeper or net or combinational node or node

Warning (332174): Ignored filter at mi.sdc(38): pll_clk25m could not be matched with a port or pin or register or keeper or net or combinational node or node

Warning (332174): Ignored filter at mi.sdc(39): pll_clk62m5 could not be matched with a port or pin or register or keeper or net or combinational node or node

Warning (332174): Ignored filter at mi.sdc(40): pll_clk20m could not be matched with a port or pin or register or keeper or net or combinational node or node

Warning (332174): Ignored filter at mi.sdc(66): CLK50M_PLL could not be matched with a clock

Warning (332049): Ignored set_clock_groups at mi.sdc(66): Argument -group with value CLK50M_PLL could not match any element of the following types: ( clk )

Info (332050): set_clock_groups -exclusive -group {CLK50M_PLL}

Warning (332174): Ignored filter at mi.sdc(67): CLK25M_PLL could not be matched with a clock

Warning (332049): Ignored set_clock_groups at mi.sdc(67): Argument -group with value CLK25M_PLL could not match any element of the following types: ( clk )

Info (332050): set_clock_groups -exclusive -group {CLK25M_PLL}

Warning (332174): Ignored filter at mi.sdc(68): CLK62M5_PLL could not be matched with a clock

Warning (332049): Ignored set_clock_groups at mi.sdc(68): Argument -group with value CLK62M5_PLL could not match any element of the following types: ( clk )

Info (332050): set_clock_groups -exclusive -group {CLK62M5_PLL}

Warning (332174): Ignored filter at mi.sdc(69): CLK20M_PLL could not be matched with a clock

Warning (332049): Ignored set_clock_groups at mi.sdc(69): Argument -group with value CLK20M_PLL could not match any element of the following types: ( clk )

Info (332050): set_clock_groups -exclusive -group {CLK20M_PLL}

Warning (332049): Ignored set_false_path at mi.sdc(79): Argument <from> is an empty collection

Info (332050): set_false_path -from [get_clocks CLK62M5_PLL] -to [get_clocks CLK62M5_SYS]

Warning (332049): Ignored set_false_path at mi.sdc(80): Argument <to> is an empty collection

Info (332050): set_false_path -from [get_clocks CLK62M5_SYS] -to [get_clocks CLK62M5_PLL]

---------------------------------------------------------------------------------------------------------------------------------

 

 

SreekumarR_G_Intel
299 Views

Would it possible to provide the design files via email or IPS case ?

 

Thank you,

 

Regards,

Sree

SreekumarR_G_Intel
299 Views

one more thought, would it possible to change the pin allocation and try , Speically to Regional clk pins ?

Thank you,

 

Regards,

Sree

SreekumarR_G_Intel
299 Views

Can i know update on this issue ?

 

Thank you ,

 

Regards,

Sree

Reply