I have a design using 10AX057N4F40E3SG compiled with Quartus Prime Standard 17.1，If I don't change anything just do several compiles, some of the compile results work correctly,som of the compile results don't work. For the error compile results , I find the following strange thing: one signal named 'ram_rd' is connected to the rden port of a dual-port RAM,and at the same ,this signal is also connected to the rdreq port of a FIFO, the RAM and FIFO work in the same clock domain. In SiganlTapII, I can see the signal at the rdreq port of FIFO works(goes to high), and at the same time ,signal at the rden port of RAM keep low. IT is surely a fiiter error. How to fix the problem?
we are doing some tests, please wait for result. It maybe need a little bit of time. Does Intel have any suggestions? By now , we found that same clock gives to read port and write port, problem would still happen. A backup ram with same reads and writes, data would change too. Same writes to a backup ram and different reading operations with repect to the original ram to read port, data could be fine. It is very strange.
Is this service request public to everyone who visits this community? I pass the source code request to my boss, They want to know how to keep our source code safely only to Intel, and not public to others.