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Altera_Forum
Honored Contributor I
979 Views

Fitter can't place 1 fractional PLL

Hi, 

 

we have a Cyclone V SX design that fails to compile because the fitter can't place 1 fractional PLL. I have compiled the design succesfully previously, but after I added two 2-lane HiSPi (LVDS) inputs to design the fitter fails. It seems that the LVDS I/O-banks (5A, 5B ) doesn't have enough PLLs since two PLLs are needed for the LVDS_RX-blocks. Has anybody any ideas how to solve this issue? 

 

Any help appreciated. 

Joonas
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2 Replies
Altera_Forum
Honored Contributor I
73 Views

Hi Joonas, 

 

maybe you use just one LVDS_RX block with two channels or the "Use External PLL" option to share one PLL between the LVDS_RXs and other clocks. 

 

regards 

Jens
Altera_Forum
Honored Contributor I
73 Views

 

--- Quote Start ---  

Hi Joonas, 

 

maybe you use just one LVDS_RX block with two channels or the "Use External PLL" option to share one PLL between the LVDS_RXs and other clocks. 

 

regards 

Jens 

--- Quote End ---  

 

 

 

I guess that we cannot share the PLL between the LVDS-inputs since the the LVDS-clocks come from two seperate image sensors that aren't syncronized between each other. Actually we have four image sensors so we would need four different PLLs and four different LVDS_RX-blocks. I'm not sure if this is possible with Cyclone V-device.
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