Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

Fitter error: 14566

PKhan8
Beginner
638 Views

I got an error 14566 : Could not place 1 periphery component(s) due to conflicts with existing constraint (1 fractional PLL(s)).

How can i fix it?

Thanks.Untitled.png

0 Kudos
4 Replies
sstrell
Honored Contributor III
246 Views

Without knowing anything about the design or even the target device, it's not really possible to diagnose this. Can you provide more details or post the project?

 

You can also expand the error message to see exactly what the conflict is.

 

#iwork4intel

AnandRaj_S_Intel
Employee
246 Views

Also, if possible share your design which will be ease our job of replicating the scenario.

PKhan8
Beginner
246 Views

Excuse me, this is projet which got error above.

I got this error after i had assigned PINs to implement it on DE1_SoC_mtl2(CycloneV) Kit

Can you help me fix it, please?

Sorry for my bad English

 

AnandRaj_S_Intel
Employee
246 Views

​Hi @PKhan8​ ,

 

Check clk_50 pin assignments.

Clock pin should be AF14/AA16/Y26/K14.

After changing the clock pin, I can run fitter successfully. 

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

 

Regards

Anand

 

Reply