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Altera_Forum
Honored Contributor I
925 Views

Fix current auto pin fit to prevent future chang

Excuse me if my question is silly. I am pretty new to Quartus. 

 

As I read from an article, it suggests to let quartus fits the pins instead by myself to avoid problem of signal quality. The quartus creats *.pin file to list the fit of pin-out after compilation. I found, it seems some change of HDL code may cause the change of pins fit. I know that I can fix the pin fit manually by the Pin Planner tool of quartus according the pins in .pin file one by one. 

 

My question is... Is there a method to import the .pin file, let those auto fit pins become user asignments? I know there is a function of "Show Fitter Placement" in the Pin Planner, but it does not seem the function I am looking for. 

 

Thanks
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7 Replies
Altera_Forum
Honored Contributor I
57 Views

You open this dialog box by clicking Back-Annotate Assignments on the Assignments menu. 

 

Allows you to copy device and resource assignments made during compilation into the Quartus II Settings File (.qsf), thereby preserving the current fit for future compilations. You can use the Back-Annotate Assignments dialog box (Default type) to preserve pin, cell, routing, or device assignments, or you can use the Back-Annotate Assignments dialog box (Advanced type) to preserve LogicLock regions and employ more advanced back-annotation options. You can select the back-annotation type in the Back-annotation type list.
Altera_Forum
Honored Contributor I
57 Views

I also don't agree with letting Quartus fit the pins instead of you. I usually do a combination, but in reality Quartus doesn't know what your board layout is. So if you have a flash device above the FPGA, make sure the flash interface pins are put there. If Quartus puts them up there but they're in the reverse direction of the way the flash is laid out(resulting in a tornado board route), then flip them. I feel designers have more information and are smarter about this then Quartus. 

 

Is what Quartus can do is fit for timing. So if you're flash comes in and needs to feed an output pin in one cycle, it won't place them on opposite sides of the FPGA. The nice thing is that if you put them on opposite sides, and have entered timing constraints, you'll get paths with negative slack(in red) alerting you to the issue.
Altera_Forum
Honored Contributor I
57 Views

 

--- Quote Start ---  

You open this dialog box by clicking Back-Annotate Assignments on the Assignments menu. 

 

Allows you to copy device and resource assignments made during compilation into the Quartus II Settings File (.qsf), thereby preserving the current fit for future compilations. You can use the Back-Annotate Assignments dialog box (Default type) to preserve pin, cell, routing, or device assignments, or you can use the Back-Annotate Assignments dialog box (Advanced type) to preserve LogicLock regions and employ more advanced back-annotation options. You can select the back-annotation type in the Back-annotation type list. 

--- Quote End ---  

 

 

Yes, this is right the function I am looking for. Thank you very much! 

 

 

--- Quote Start ---  

I also don't agree with letting Quartus fit the pins instead of you. I usually do a combination, but in reality Quartus doesn't know what your board layout is. So if you have a flash device above the FPGA, make sure the flash interface pins are put there. If Quartus puts them up there but they're in the reverse direction of the way the flash is laid out(resulting in a tornado board route), then flip them. I feel designers have more information and are smarter about this then Quartus. 

 

Is what Quartus can do is fit for timing. So if you're flash comes in and needs to feed an output pin in one cycle, it won't place them on opposite sides of the FPGA. The nice thing is that if you put them on opposite sides, and have entered timing constraints, you'll get paths with negative slack(in red) alerting you to the issue. 

--- Quote End ---  

 

 

And the fitter mixed up I/O pins of all 7 ports in my design. Looks chaos XD.
Altera_Forum
Honored Contributor I
57 Views

Look at the pin planner. (Assignments -> Pin Planner.) You can drag busses and have it auto-fill in directions, or you can grab individual pins and quickly place them. It's really the way to go, and you can run Processing -> Start -> I/O Assignment Analysis to verify a good number of live checks(like pins requiring different I/O standards in the same bank). As I said earlier, Quartus just doesn't know enough about your board to do a good job(and it sounds like you're getting a bad job anyway), so I would recommend using this tool.

Altera_Forum
Honored Contributor I
57 Views

Useful advice. Thank you, Rysc!

Altera_Forum
Honored Contributor I
57 Views

Ah... That is strange... I can not drag them from the left Node Name list. Do I miss something? I have pressed down the Assign Down button. 

 

My Quartus II version 7.1 Build 178 06/25/2007 SJ Web Edition 

 

---- 

 

I know how to drag it now. It is tricky. Give it a click to select it first, the color will toggle, then release mouse button and click on it again to drag it.
Altera_Forum
Honored Contributor I
57 Views

Rysc; 

 

Looks like we killed this one, good working together. 

 

Am interesting aside, while reading your comments you referred to a term I had not heard of before, "If Quartus puts them up there but they're in the reverse direction of the way the flash is laid out(resulting in a tornado board route), then flip them." 

 

"Tornado". In my board routing days, we referred to these as "Haystacks". 

 

Interesting difference in visuals. 

Cheers, 

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