Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15553 Discussions

Fixed--Cannot view RTL netlist

DNguy4
Beginner
983 Views
0 Kudos
2 Replies
KhaiChein_Y_Intel
99 Views

Hi,

 

Could you give some details/description of your question?

Thanks

 

 

DNguy4
Beginner
99 Views

I was able to do a full compilation on my design but i could not view the RTL netlist. I found out that my colleague changed some settings in Assignments/Setting. I reset those settings to default and i am able to view the RTL netlist now.

Reply