Floating-Point IP for FIFO Buffer

[Shainy]

Hi,

I'm suing Quartus Prime Lite 18.1 and using a Cyclone V device. I was searching for a floating-point ip for a fifo buffer, but was unable to find one. But I did see a fifo buffer ip  'FIFO' under on chip memory. Could someone confirm if this could be used for floating point values as well, or if there is a different ip that I could use? Thanks in advance!

Best Regards,

Shainy

[CheePin_C_Intel]

Hi,

As I understand it, you have some inquries related to CV floating IP. Sorry as I am not clear with the FIFO buffer that you are referring to. For your information, you may refer to the Floating-Point IP Cores User Guide (https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_altfp_mfug.pdf) for the supported floating point IPs in CV device to see if any of them suit your target application. Note that I am unable to locate any specific FIFO buffer keyword in the user guide.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

[Shainy]

Hi Chee Pin,

Thank you so much for your reply. Yes, as you've mentioned there wasn't any ip mentioned on the user guide, so I guess there is no ip for it. But I tried running the the following code to build a buffer, and there were no errors that came up. But, when I give in values on the test bench and simulate through Modelsim, it gets rounded to the closest integer. Is there anything wrong with my code or is there any advice that I could use, to display a floating-point number instead of the closest integer value? 

`define BUF_WIDTH 3
`define BUF_SIZE ( 1<<`BUF_WIDTH )

module FifoBuffer2( clk, reset, in_x, out_x, write, read, emp, full);

input reset, clk, write, read;
input [8:0] in_x;
output [8:0] out_x;
output emp, full;
reg[8:0] out_x;
reg emp, full;
reg[`BUF_WIDTH -1:0] rd_ptr, wr_ptr;
reg[8:0] buf_mem[`BUF_SIZE -1 : 0];

always @(posedge clk)
begin

if( write && !full )
buf_mem[ wr_ptr ] <= in_x;

else
buf_mem[ wr_ptr ] <= buf_mem[ wr_ptr ];
end
always @(posedge clk) begin
if( reset )
begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else
begin
if( !full && write )wr_ptr <= wr_ptr + 1;
else wr_ptr <= wr_ptr;

if( !emp && read ) rd_ptr <= rd_ptr + 1;
else rd_ptr <= rd_ptr;
end

end
endmodule

[CheePin_C_Intel]

Hi,

Thanks for your update. For your information, I am not really a design specialist and thus could not really comment on your observation with the simulation. Sorry for the inconvenience.

As I search through the Forum, I found the following post which might be handy to you:

https://community.intel.com/t5/Intel-Quartus-Prime-Software/float-data-format-are-simulated-in-Modelsim/td-p/216048

You can take a look to see if it is helpful. If not, you might want to try consult Modelsim to see if they have any insight.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

[CheePin_C_Intel]

Hi,

As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.