For cyclone 4 LVDS_TX IP, how to config Frequency of tx_clkout = tx_out as outclk divide factor(B) couldn't be set to 1 - Intel Community

Intel® Quartus® Prime Software

Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

For cyclone 4 LVDS_TX IP, how to config Frequency of tx_clkout = tx_out as outclk divide factor(B) couldn't be set to 1

544 Views

Link Copied

2 Replies

513 Views

Hi Silu

You can set the data rate and the outclock divide factor (B) accordingly to achieve tx_out and tx_outclock requirement.

Thanks.

Eng Wei

Copy link

513 Views

Hi Silu

Let me know if you have any question before we proceed to close the ticket. Thanks.

Eng Wei

Copy link

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.