Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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For cyclone 4 LVDS_TX IP, how to config Frequency of tx_clkout = tx_out as outclk divide factor(B) couldn't be set to 1

SYou1
Beginner
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EngWei_O_Intel
Employee
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Hi Silu

 

You can set the data rate and the outclock divide factor (B) accordingly to achieve tx_out and tx_outclock requirement.

 

Thanks.

Eng Wei

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EngWei_O_Intel
Employee
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Hi Silu

 

Let me know if you have any question before we proceed to close the ticket. Thanks.

 

Eng Wei

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