I am hoping someone may have an answer to a problem I have wrestled with for a long time.
I make a lot of use of SignalTap to analyze what is going on inside my FPGA design but so often I find that Quartus has optimized the required signal away and it cannot therefore be included as a 'node' in SignalTap.
I have tried applying the attributes 'keep' 'preserve' and 'noprune' but none of them work. This normally means that I compile the design, go to SignalTap and find the node isn't listed so I then have to write some dummy VHDL code to make use of the signal, re-compile and try again. This is really annoying if it's a big design and takes 5 - 10 minutes to compile...
The only way I have found to keep a signal is to use it to drive a pin of the chip, luckily in the design I'm working on at the moment I have a number of pins on the chip (5CEBA2F17C8N) that are not tracked to anything so I can name them as 'Hold00' to 'Holdxx' and assign signals to them, but this seems ridiculous!!
Surely there is a way to tell the optimization stage of the compilation that I want to keep a signal, even if it is not used in the internal logic?
Any help or suggestions would be gratefully received
I think it may depend on how you add signals to your Signal Tap.
First you do not need to run the whole compilation, just elaboration is enough (saves a lot of time).
Then when you use the Signal Tap's node finder, select "Signal Tap: pre-synthesis" in the filter options.
Save and do full compilation this time. It should work. At least this is what I do, though I do not think I have unused internal logic to monitor in my designs.
Hope that helps
I'm presuming you are using Quartus Standard because that's a Cyclone V device. Pro now has the new "preserve for debug" feature just for this issue.
Are you trying to tap pre-synthesis or post-fit nodes? I'm presuming post-fit because if you tap pre-synthesis nodes, they should be preserved through compilation. If you can, try using the Signal Tap pre-synthesis filter in the Node Finder when you tap nodes and see if that makes a difference.
There a few suggestions have been provided by MathiasB and sstrell to your query.
Kindly try those suggestions and do let me know if the issue has been addressed.
Please let me know if you have any further question.
Hi, replying to all of you who have been kind enough to respond:
I have tried the suggested options and none of them seem to work.
To be clear I am using Quartus Prime Lite so is it likely that these options may be "crippled" in this free version?
To give an example:
I am working with serial bit streams that consist of LRCLK (96kHz square wave), an SCLK (256 * LRCLK) and a serial stream of data bits at SCLK frequency (some may recognise this as a TDM8 digital audio stream).
SCLK is the highest frequency I have in the design (24.576 MHz) so to capture the signals in SignalTap I use a 4* PLL to give me a Global 98.304 MHz clock, SignalTap is the only part of the design that uses this Global clock.
After compiling; this clock is not presented as an available node for SignalTap's clock configuration, I have tried every one of the available filters in the Node Selector but there's nothing.
If I go back to the VHDL code and connect Global_98 to a device pin and then re-compile, the node is now available and I can select it in SignalTap.
HOWEVER; if I then go back to the VHDL code and delete Global_98's connection to a pin then after compilation SignalTap now shows Global_192 in red text which I take to mean this node has been optimized out! (even though SignalTap is using it) and if I try to capture data with SignalTap is says "waiting for clock".
This is not the only case where nodes are removed by optimization but it is probably the most frustrating.
As I mentioned, I have been "working around" this behaviour by applying signals to device pins to force them to remain but I don't understand why my extensive use of "keep" "preserve" and "noprune" don't achieve what I expect of them.
Thanks for you replies and interest in my problem
My problems with this optimising gets worse...
I have just been looking at some signals with SignalTap and a "write strobe" signal that I generate is designed to be active low for 1 cycle in every 128.
I have fed this signal to a pin and examined it with an oscilloscope and it is exactly what I expect it to be ------|_|---------
_BUT_ when I capture the same node in SignalTap it is shown upside down, ________|-|_____________
What is SignalTap doing to show my signals incorrectly ?
How can I check if my logic is working the way it is designed to work if I can't trust what SignalTap is showing me ?
Please, any advise, I'm going a bit crazy here
A lot going on here. First, Signal Tap is not crippled in the Lite edition, so that's not an issue here.
Also, sanity check: you are trying to select the clock in the sampling clock setting on the right side of the Signal Tap window where the configuration options are, not in the main Node List on the left in the Setup tab.
I'm presuming "Global_98" is what you have named the 98 MHz clock coming from the PLL and you are saying that that clock is normally not present anywhere in your HDL code, which would be why you think it is getting optimized away and not appearing in either the Signal Tap pre-synthesis or post-fit Node Finder filters.
If indeed that is the case, though I've never seen this before, you could simply add a virtual pin assignment in the Assignment Editor for the PLL output instead of connecting to a physical pin. That would preserve the signal. I guess I've never generated a clock explicitly as the sampling clock for Signal Tap, always using a a clock domain in the design instead.
I'm not sure what "Global_192" is or what that is referring to.
As for the inverted signal, where exactly are you tapping it? If it's active low, perhaps you've accidentally tapped before an inversion of the signal.
thanks for your considered reply.
Thanks for confirming that my problems are not because I am using the Lite edition.
You are correct that Global_98 is the node name for my 98 MHz clock signal, it is the output of the PLL unit fed through a ClkCtrl unit (both from the IP catalogue). I am using the ClkCtrl unit because I saw some comments in an online document that these were used to apply signals onto the chips internal clock distribution tracks and that clocking would be better if it were done this way. I have however had the same problems when not using ClkCtrl units.
The reference to Global_192 was my mistake, I did previously name the clock output incorrectly. You are also correct that I am trying to select the clock in the sampling clock setting on the right side of the Signal Tap window.
Thank you for the tip about adding virtual pins in the Assignment Editor, I didn't know that I could do that, it will prove useful on other designs where I don't have spare real pins to make use of.
I think I resolved the inverted signal problem by selecting nodes using the "SignalTap pre-synthesis" filter in the node selector. The signal is originally generated in my top level entity and then fed into a "component". Originally I had tapped the signal where it was generated (using the SignalTap post-fitting filter) but I subsequenty changed to tap it inside the component definition and using the pre-synthesis filter and it was then displayed the correct way up.
thanks for your input
I happen to have a design in Quartus Prime Lite 20.1 that has a PLL with multiple outputs, but only one is actually used in the design.
I could see one of the unused clock outputs in Signal Tap node finder and select it; add a signal to monitor and recompile. I haven't seen any complain by Quartus, so I assume your case should be working too.
I cannot test this on an actual board though, but at least I can see that an unconnected PLL output can be selected in Signal Tap.
Could you parse the Quartus (critical) warnings for anything related to this clock when it is not connected to anything (other than Signal Tap)? Even if it doesn't seem much?
As for the problem of the inverted signal, I don't know much more. I suppose the write_strobe signal is not connected to a differential pair and you are not monitoring two different poles? (Sorry if the question is dumb, but I have found Signal Tap to be reliable in my use cases).
thanks for your suggestions.
I resolved the issue with the inverted signal thanks for your suggestions. I used the "pre-synthesis" filter in SignalTap's node selector and tapped the signal inside a "component" rather than in the top-entity where it is generated. This subsequently displayed it the right way up (see my reply to sstrell...).
I will do as you suggest and look for references in the Quartus (critical) warnings.
No question is dumb and thank you for asking them, a friend of mine's Dad used to say "the only dumb question is the one you don't ask", I appreciate your input.
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