Forcing FPGA signal using SignalTap Logic Analizer

[Altera_Forum]

Hi. 

I am looking some possibility to force Altera's internal signals (wires or registers) using Quartus tools. As I remember, in Xilinx development tool ISE I could assign values to internal signals using ChipScope tool. I suppose, Altera should also have similar possibility. Someone used it? And how? Thank you. Dima

[Altera_Forum]

Yes, it is called SignalTap. 

It is included free with the subscription version of your tools.  There should be free WEB based training on the Altera Web site under education.

[Altera_Forum]

--- Quote Start ---  Yes, it is called SignalTap. It is included free with the subscription version of your tools.  There should be free WEB based training on the Altera Web site under education.  --- Quote End ---    Yes, I familiar with SignalTap Embedded Logic Analizer. But this tool can only acquire data from FPGA, and I didn't find any option to FORCE Altera internal registers with SignalTap, I could only to sample it.

[Altera_Forum]

I am afraid you can't...:(

[Altera_Forum]

The only option to force an internal signal is to use a Source & Probe instance and add a multiplexer to the design, that switches each individual signal to a source & probe output.

[Altera_Forum]

--- Quote Start ---  ... use a Source & Probe instance...  --- Quote End ---    For the documentation, see the Quartus handbook, Volume 3, Section V, Chapter 17, "Design Debugging Using In-System Sources and Probes".   Depending on what you are trying to accomplish, the ECO design flow might work. It lets you make/change some routing connections, change LUT contents, etc. without running a full recompilation. That's covered in Volume 2, Section IV, Chapter 13, "Engineering Change Management with the Chip Planner".

[Altera_Forum]

I think, that's the tool I looked for - Source & Probe. 

I'll check it out. Thank you.