Freezing partion layout exactly in Cyclone III (not LS)

[Altera_Forum]

Part: EP3C120F484I7 (Cyclone III 120K) 

Quartus version 9.1SP2 subscription  I have a small region, the final output to a high-speed (>200MHz) external DAC, which is apparently sensitive to port skew. I've not had much luck in solving this with constraints alone.   I'm attempting to use LogicLock to, um, lock the logic to a skinny region up against the relevant ports. I've got a very happy layout and I'd like to preserve it. I've turned on incremental compile, and set rapid recompile to "highest preservation." Nothing involving this module, or any module connecting to it, has changed or is likely to change. And yet, when changing a distant module with no reasonable connection, the layout in the "locked" module can change dramatically.   Besides perhaps needing to go to a later version of Quartus, what can I do to lock this puppy down? I'm reluctant to change Quartus versions without good reason, as this is built off an old design and I'd rather not open up new and different cans of worms.   Is there some way to say "do not ^$^%&$ change this at all"?

[Altera_Forum]

Put the logic in its own hierarchy, make it a design partition and set it to Post-Fit. When you get a build with good timing, right-click and export the partition as a .qxp. Then add that to your project instead of the source HDL for that hierarchy. (Continue to keep it as a post-fit partition). That was brief, but there should be lots of posts/documentation on partitions.

[Altera_Forum]

Thanks. That was exactly the info I needed.

[Altera_Forum]

--- Quote Start ---  Put the logic in its own hierarchy, make it a design partition and set it to Post-Fit. When you get a build with good timing, right-click and export the partition as a .qxp. Then add that to your project instead of the source HDL for that hierarchy. (Continue to keep it as a post-fit partition). That was brief, but there should be lots of posts/documentation on partitions.  --- Quote End ---    Thanks for the sharing. This info is helpful.

[Altera_Forum]

--- Quote Start ---  Put the logic in its own hierarchy, make it a design partition and set it to Post-Fit. When you get a build with good timing, right-click and export the partition as a .qxp. Then add that to your project instead of the source HDL for that hierarchy. (Continue to keep it as a post-fit partition). That was brief, but there should be lots of posts/documentation on partitions.  --- Quote End ---    Great info sharing.

[Altera_Forum]

Yes, the Altera documentation is particularly impenetrable, even by Altera standards. This was clear. 

 One other thing I learned. At least in the versions I tried, you cannot turn on both incremental compilation and rapid compile. In 9.1 it simply aborts with no good reason. In later versions you get a "don't do that" popup, probably a patch for the abort. Just stick with the incremental compile.