GUI for camera pipeline

[Altera_Forum]

Hi everyone, 

 I would like to build a complete system in which I can connect a camera and accelerate the processing via FPGA for my cyclone-5 FPGA on Terasic DE-1 Board. In order to that I want to have a gui support and preferably install openCV. Besides that I have very little time, I don't have any experience in embedded linux or this HPS system design. Any help in this matter is appreciated!   what do i have: +Terasic provides these: * Sd card image consisting of a yocto operating system without packet manager for OpenCL based acceleration.  => FAT partition consists of : opencl.rbf, socfpga.dtb, u-boot.src, zimage * An ubuntu and an lxde desktop installation based on xillinux. Unfortunately, both of them doesn't have driver files.   => FAT partition consists of : socfpga.dtb, soc_system.rbf, uImage link: http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=205&no=836&partno=4 * Real time library source files for cyclone-5 and bsp files for de1.  +Rocketboards: * arrowsoc opencl based yocto  => FAT partition consists of : opencl.rbf, socfpga.dtb, u-boot.src, zimage  link: https://rocketboards.org/foswiki/view/documentation/arrowsockitopencl * opencl based System for sodia  link: https://rocketboards.org/foswiki/view/projects/sodiaboardopencl_en * golden system reference design to build yocto based HPS (Hard Processor Based System) for Cyclone5  link: https://rocketboards.org/foswiki/view/documentation/gsrd141   what have i learn so far:  +First of all there are these FPGA Configuration Schemes: (via MSEL switches)  DE1_soc_user_manual : ftp://ftp.altera.com/up/pub/altera_material/boards/de1-soc/de1_soc_user_manual.pdf  =>  10010 -> as: FPGA configured from EPCQ (default)  01010 -> fppx32 : FPGA configured from HPS software: Linux  00000 -> fppx16 : FPGA configured from HPS software: U-Boot, with image stored on the SD card  =>  Altera devices offer fast passive parallel (FPP) configuration with different data bus widths: 8 bit data width (FPP x8), 16 bit data width (FPP x16), and 32 bit data width (FPP x32)  link: https://www.altera.com/support/support-resources/support-centers/devices/cfg-index/cfg-fpp.html  *** So this modes determines whether the FPGA is configured from the software and if so configuration speed   and booting scheme of the HPS if I understand correctly. Provided OpenCL based operating systems run on FPPx32 mode.  + If I work inf FPPx32, I have to have a bootloader (u-boot) and zImage linux as I understand.  In these case, these are main steps:  1. Create a Device Tree Blob (.dtb)  2. Generate Raw Binary File (.rbf)   3. Bootloader (u-boot.src for the provided opencl image)   4. Install Linux and Real-time library onto the operating system.  final questions: + AOC code generation automatically builds the system (via sopc builder) and also generates the .rbf file, which informs the operating system and Hal about the underlying hardware. So is this hardware always fix for the opencl code generation and is there anyway to add frame buffers for vga for example? If so how is the fastest way?