Gate level sim QTSII 10.1 / Modelsim 6.6c (both free)

[Altera_Forum]

Hello, 

 I'm a newbie in fpga programming although I 've been in the semicon industry for a while (analog design). My application needs to capture data from a multichannel-high speed ADC (40Msps, 12bit, LVDS)    Firstly I downloaded quartus 10 and I got frustrated to get an RTL simulation for the ALTLVDS function (not having into account the bug of megawizard not showing up). After tried googling, tutorials and forums, I downloaded the 10.1 version and got RTL sim working.I'm using a simple test bench for driving the inputs. It works.   Now I’m looking for getting a working gate level simulation. My steps are Full compilation and then tools->Run EDA simulation tool->EDA gate level simulation (transcript attached). The design is a simple AND gate (two inputs and one output).    Before advising me to read the full verification chapter in quartus manual I would like to get a brief tutorial for getting the gate level sim working. I wouldn’t be posting if all the info in google and/or altera forums wouldn’t have been of much help as most of it refers to QTS 9.1 and below.     Thanks in advance for your kindly help!  Please, is there anyone that can give me some hints/help regarding the issue. Any reading material? I'll appreciate your help. Most of the threads that I've seen with this question are still unswered.

[Altera_Forum]

For those of you interested in running a gate level sim using the Quartus tools (v10.1, modelsim 6.6c): 

 1 - Generate test bench: Go to Processing->Start-> Start Test bench writer template writer  2 - Modify the test bench for driving the inputs of your design (lots of info in google)  3 - Include the test bench for automatically create the modelsim TCL script  Go to Assigments->sesttings->simulation Then check "compile test bench", click on "test benches", a new window pops up, click on "new" On the new window, fill in "test bench name" and "top level module in test bench" with <your_design_name>_vhd_tst Check on "use test bench to perform VHDL timing simulation" and type i1 ( or whatever region you may be using but defaults to i1 if not changed) on "desing instance name in test bench". Pickup the vht file you presviuosly saved clicking in "..." of the file name section. Click on "add" Click many times ok and you will be ready for running either and RTL or a gate simulation  Hope it helps others new to Quartus 10